Foundational theory

Fault Models is central to ATPG & Pattern Generation. Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality. Senior DFT engineers tie metric movement to architecture assumptions, constraints, and silicon evidence rather than isolated tool output.

Core concepts explained

• Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality.

• Primary metric: stuck-at / transition / bridge coverage, untestable fault ratio

• Primary artifact: fault coverage report, fault class breakdown, untestable list

• Owners: ATPG owner, DFT architect, quality owner

• Controllability and observability must be explicit

• Production-quality requires reproducible pattern and tester tags

Why this matters at release

At release, Fault Models issues can create coverage escapes, unstable production bins, or long debug loops. ATPG is a model-driven search constrained by legal test behavior.

Mental model

fault model ladder
1) stuck-at
2) transition
3) bridge/path-delay/cell-aware

Each rung improves quality and increases runtime/pattern cost.

Worked intuition

1. Name failing metric and scenario context (mode, lot/corner, program).

2. Open stuck-at / transition / bridge coverage, untestable fault ratio trend and isolate dominant failing bucket.

3. Trace architecture assumptions and legality constraints.

4. Check compression, clocking, and unknown handling dependencies.

5. Collect fault coverage report, fault class breakdown, untestable list and confirm run tags.

6. Classify issue: model/constraint, physical/test setup, or real defect signal.

7. Propose minimal fix and list timing/power/quality regression checks.

Common misconceptions

• Coverage percent alone proves release readiness.

• More compression always means better outcome.

• Silicon mismatch can be debugged without pattern/tester traceability.

• Shift timing and test power can be signed independently.

Visual reinforcement

Fault model stack

fault model ladder
1) stuck-at
2) transition
3) bridge/path-delay/cell-aware

Each rung improves quality and increases runtime/pattern cost.

Layer responsibilities

DFT OWNERSHIP LAYERS - Fault Models

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

ATPG quality comes from fault model choice plus legal constraints, not raw pattern volume alone.

Concept diagram

ATPG FLOW

fault model -> constraints -> generation -> simulation -> coverage closure -> signoff

Metric graph

COVERAGE GAP

target coverage
  ^
  |      o before closure
  |          o after fixes
  +---------------------> iteration

Reports and artifacts

• fault model coverage

• untestable class report

• constraint legality errors

• pattern signoff memo

Mini case study

Transition coverage stalled due to clock constraints mismatch; updated at-speed capture definitions recovered target.

Debug branches

• Classify untestable faults

• Diff ATPG constraints each run

• Pair coverage with pattern budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Theory reinforcement

ATPG is a model-driven search constrained by legal test behavior.