Interview drills

Interview Drills for Fault Models focuses on stuck-at / transition / bridge coverage, untestable fault ratio. The goal is to convert metric movement into mechanism, owner, and release decision.

PROMPT
You observe stuck-at / transition / bridge coverage, untestable fault ratio on Fault Models. Walk through diagnosis and release decision.

STRONG ANSWER
1. States context and run tags.
2. Explains mechanism: Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality.
3. Requests fault coverage report, fault class breakdown, untestable list.
4. Proposes minimal fix and regression.

WEAK ANSWER
Jumps to tool switches without evidence quality, ownership, or regression plan.

Diagram to draw on the whiteboard

Fault model stack

fault model ladder
1) stuck-at
2) transition
3) bridge/path-delay/cell-aware

Each rung improves quality and increases runtime/pattern cost.

Root-cause narrative

ROOT-CAUSE TREE - Fault Models

stuck-at / transition / bridge coverage, untestable fault ratio regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

DFT deep dive

ATPG quality comes from fault model choice plus legal constraints, not raw pattern volume alone.

Concept diagram

ATPG FLOW

fault model -> constraints -> generation -> simulation -> coverage closure -> signoff

Metric graph

COVERAGE GAP

target coverage
  ^
  |      o before closure
  |          o after fixes
  +---------------------> iteration

Reports and artifacts

• fault model coverage

• untestable class report

• constraint legality errors

• pattern signoff memo

Mini case study

Transition coverage stalled due to clock constraints mismatch; updated at-speed capture definitions recovered target.

Debug branches

• Classify untestable faults

• Diff ATPG constraints each run

• Pair coverage with pattern budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality.

Metric: stuck-at / transition / bridge coverage, untestable fault ratio