Debug Playbook for Fault Models focuses on stuck-at / transition / bridge coverage, untestable fault ratio. The goal is to convert metric movement into mechanism, owner, and release decision.
Debug aims to find the first incorrect assumption, not the loudest downstream symptom. Start with reproducibility and ownership.
ROOT-CAUSE TREE - Fault Models
stuck-at / transition / bridge coverage, untestable fault ratio regresses
|
setup changed?
/ \
yes no
| |
constraint silicon or
or ATPG physical/test path
/ \ |
SDC model chain/clock/power/diagnosis
diff diff isolate first failing signatureFreeze run tags for patterns, constraints, and tester setup.
Isolate first failing metric bucket and scenario.
Classify failure source: model, constraints, physical, or silicon.
Prove mechanism with one reduced replay or targeted run.
Apply smallest owner-controlled fix.
Re-run timing, power, and quality regression matrix.
STAFF DFT REVIEW MEMO - ATPG & Pattern Generation / Fault Models
1. Symptom
- Watched metric: stuck-at / transition / bridge coverage, untestable fault ratio
- Failing scenario: <mode/lot/corner/program>
- Pattern class: <scan/transition/compressed/BIST/JTAG>
- Tags: <constraints, patterns, tester program, netlist>
2. Mechanism hypothesis
- Primary mechanism: Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality.
- Competing hypothesis: <constraint issue, model issue, physical issue, silicon issue>
- Missing evidence: <report, replay, diagnosis trace>
3. Proposed action
- Minimal reversible change: <constraint fix, architecture tweak, pattern update>
- Expected metric movement: <delta>
- Regression risk: timing, power, quality, schedule
4. Signoff
- Re-run artifact: fault coverage report, fault class breakdown, untestable list
- Required owners: ATPG owner, DFT architect, quality owner
- Final decision: release, waive, rollback, or escalateATPG quality comes from fault model choice plus legal constraints, not raw pattern volume alone.
ATPG FLOW
fault model -> constraints -> generation -> simulation -> coverage closure -> signoffCOVERAGE GAP
target coverage
^
| o before closure
| o after fixes
+---------------------> iterationfault model coverage
untestable class report
constraint legality errors
pattern signoff memo
Transition coverage stalled due to clock constraints mismatch; updated at-speed capture definitions recovered target.
Classify untestable faults
Diff ATPG constraints each run
Pair coverage with pattern budget
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.
Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality.
Metric: stuck-at / transition / bridge coverage, untestable fault ratio
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