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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
    • Fault Models
      • Fault Models: Mechanism
      • Fault Models: Inputs & Outputs
      • Fault Models: Reports & Metrics
      • Fault Models: Debug Playbook
      • Fault Models: Worked Example
      • Fault Models: Pitfalls & Red Flags
      • Fault Models: Interview Drills
      • Fault Models: Review Checklist
      • Fault Models: Theory Deep Dive
      • Fault Models: Design Space
      • Fault Models: Expanded Case Study
      • Fault Models: Step-by-Step Walkthrough
      • Fault Models: Comparison Matrix
      • Fault Models: Software / Programmer View
      • Fault Models: Silicon PPA Impact
    • ATPG Constraints
    • Pattern Signoff
    • Coverage Closure
    • ATPG & Pattern Generation: Tricky Q&A
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Fault Models
  1. Topics
  2. Design for Test
  3. ATPG & Pattern Generation
  4. Fault Models
  5. Fault Models: Debug Playbook

DFT / ATPG · All levels

Fault Models: Debug Playbook

Debug Playbook for Fault Models.

On this page

    Debug playbook

    Debug Playbook for Fault Models focuses on stuck-at / transition / bridge coverage, untestable fault ratio. The goal is to convert metric movement into mechanism, owner, and release decision.

    Debug aims to find the first incorrect assumption, not the loudest downstream symptom. Start with reproducibility and ownership.

    Root-cause tree

    Diagram
    ROOT-CAUSE TREE - Fault Models
    
    stuck-at / transition / bridge coverage, untestable fault ratio regresses
            |
      setup changed?
        /        \
      yes         no
      |            |
    constraint    silicon or
    or ATPG       physical/test path
     /    \          |
    SDC   model    chain/clock/power/diagnosis
    diff  diff     isolate first failing signature
    1. Freeze run tags for patterns, constraints, and tester setup.

    2. Isolate first failing metric bucket and scenario.

    3. Classify failure source: model, constraints, physical, or silicon.

    4. Prove mechanism with one reduced replay or targeted run.

    5. Apply smallest owner-controlled fix.

    6. Re-run timing, power, and quality regression matrix.

    Review memo template

    Diagram
    STAFF DFT REVIEW MEMO - ATPG & Pattern Generation / Fault Models
    
    1. Symptom
       - Watched metric: stuck-at / transition / bridge coverage, untestable fault ratio
       - Failing scenario: <mode/lot/corner/program>
       - Pattern class: <scan/transition/compressed/BIST/JTAG>
       - Tags: <constraints, patterns, tester program, netlist>
    
    2. Mechanism hypothesis
       - Primary mechanism: Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality.
       - Competing hypothesis: <constraint issue, model issue, physical issue, silicon issue>
       - Missing evidence: <report, replay, diagnosis trace>
    
    3. Proposed action
       - Minimal reversible change: <constraint fix, architecture tweak, pattern update>
       - Expected metric movement: <delta>
       - Regression risk: timing, power, quality, schedule
    
    4. Signoff
       - Re-run artifact: fault coverage report, fault class breakdown, untestable list
       - Required owners: ATPG owner, DFT architect, quality owner
       - Final decision: release, waive, rollback, or escalate

    DFT deep dive

    ATPG quality comes from fault model choice plus legal constraints, not raw pattern volume alone.

    Concept diagram

    Diagram
    ATPG FLOW
    
    fault model -> constraints -> generation -> simulation -> coverage closure -> signoff

    Metric graph

    Diagram
    COVERAGE GAP
    
    target coverage
      ^
      |      o before closure
      |          o after fixes
      +---------------------> iteration

    Reports and artifacts

    • fault model coverage

    • untestable class report

    • constraint legality errors

    • pattern signoff memo

    Mini case study

    Transition coverage stalled due to clock constraints mismatch; updated at-speed capture definitions recovered target.

    Debug branches

    • Classify untestable faults

    • Diff ATPG constraints each run

    • Pair coverage with pattern budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality.

    Metric: stuck-at / transition / bridge coverage, untestable fault ratio

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    See also

    • Fault Models: Mechanism
    • Fault Models: Inputs & Outputs
    • Fault Models: Pitfalls & Red Flags