Inputs and outputs contract

Inputs & Outputs for Fault Models focuses on stuck-at / transition / bridge coverage, untestable fault ratio. The goal is to convert metric movement into mechanism, owner, and release decision.

Treat these as a release contract. Ambiguity here creates expensive debug loops because teams optimize against different assumptions.

INPUTS
  - scan/ATPG architecture and constraints
  - fault model and quality target policy
  - pattern generation config + tester limits
  - timing/power/physical assumptions

OUTPUTS
  - quality metrics and closure status
  - signed artifacts and owner approvals
  - diagnosis evidence for residual risk
  - release, waiver, or escalation decision

Flow sequence

DFT FLOW - Fault Models

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: stuck-at / transition / bridge coverage, untestable fault ratio

Ownership map

OWNERSHIP MAP - Fault Models

artifact              owner
----------------      -----------------
architecture/report ATPG owner
constraints/setup   DFT architect
physical/test       quality owner

Name an owner for each failing metric cluster.

DFT deep dive

ATPG quality comes from fault model choice plus legal constraints, not raw pattern volume alone.

Concept diagram

ATPG FLOW

fault model -> constraints -> generation -> simulation -> coverage closure -> signoff

Metric graph

COVERAGE GAP

target coverage
  ^
  |      o before closure
  |          o after fixes
  +---------------------> iteration

Reports and artifacts

• fault model coverage

• untestable class report

• constraint legality errors

• pattern signoff memo

Mini case study

Transition coverage stalled due to clock constraints mismatch; updated at-speed capture definitions recovered target.

Debug branches

• Classify untestable faults

• Diff ATPG constraints each run

• Pair coverage with pattern budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality.

Metric: stuck-at / transition / bridge coverage, untestable fault ratio