Pitfalls and red flags

Pitfalls & Red Flags for Fault Models focuses on stuck-at / transition / bridge coverage, untestable fault ratio. The goal is to convert metric movement into mechanism, owner, and release decision.

• Coverage improves while diagnosis quality degrades.

• Pattern count drops but test escapes rise.

• Shift timing passes while capture timing regresses.

• Power fixes alter quality behavior without retest.

• Owner handoff is unclear for recurring failures.

Layer responsibility check

DFT OWNERSHIP LAYERS - Fault Models

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

ATPG quality comes from fault model choice plus legal constraints, not raw pattern volume alone.

Concept diagram

ATPG FLOW

fault model -> constraints -> generation -> simulation -> coverage closure -> signoff

Metric graph

COVERAGE GAP

target coverage
  ^
  |      o before closure
  |          o after fixes
  +---------------------> iteration

Reports and artifacts

• fault model coverage

• untestable class report

• constraint legality errors

• pattern signoff memo

Mini case study

Transition coverage stalled due to clock constraints mismatch; updated at-speed capture definitions recovered target.

Debug branches

• Classify untestable faults

• Diff ATPG constraints each run

• Pair coverage with pattern budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality.

Metric: stuck-at / transition / bridge coverage, untestable fault ratio