Extended case study

Release review: scan cell legality rate, scan replacement ratio, scan DRC count regresses after a test-flow update touching Scan Cell Architecture.

Background

Team had prior signoff, then a new program/config introduced regressions in selected buckets.

Symptoms observed

• scan cell legality rate, scan replacement ratio, scan DRC count regression

• Mismatch between simulation and tester

• Escalation without clear owner

Investigation timeline

1. Hour 0: freeze pattern set, constraints, and tester program tags

2. Hour 1: isolate first failing bucket by mode/lot

3. Hour 2: verify legality and constraints assumptions

4. Hour 3: correlate with physical/timing/power context

5. Hour 4: choose minimal reversible fix

6. Hour 5: run full signoff regression matrix

7. Hour 6: publish decision memo and owners

Root cause

Root cause tied to Scan Cell Architecture: Scan insertion replaces functional flops with scan-capable cells so internal state becomes controllable and observable in test mode.

Fix and validation

• Apply bounded fix with owner

• Re-run scan insertion report, scan DRC log, scan replacement summary

• Re-validate quality, timing, and test power

Lessons learned

• Tag every run artifact

• Mechanism first, command second

• Close with explicit release decision

CASE STUDY - Scan Cell Architecture
baseline metric / regressed metric / post-fix metric

Sequence under stress

DFT FLOW - Scan Cell Architecture

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: scan cell legality rate, scan replacement ratio, scan DRC count

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Scan insertion replaces functional flops with scan-capable cells so internal state becomes controllable and observable in test mode.

Metric: scan cell legality rate, scan replacement ratio, scan DRC count