Scan Cell Architecture: Interview Drills

Interview drills

Interview Drills for Scan Cell Architecture focuses on scan cell legality rate, scan replacement ratio, scan DRC count. The goal is to convert metric movement into mechanism, owner, and release decision.

PROMPT
You observe scan cell legality rate, scan replacement ratio, scan DRC count on Scan Cell Architecture. Walk through diagnosis and release decision.

STRONG ANSWER
1. States context and run tags.
2. Explains mechanism: Scan insertion replaces functional flops with scan-capable cells so internal state becomes controllable and observable in test mode.
3. Requests scan insertion report, scan DRC log, scan replacement summary.
4. Proposes minimal fix and regression.

WEAK ANSWER
Jumps to tool switches without evidence quality, ownership, or regression plan.

Diagram to draw on the whiteboard

Mux-DFF scan cell behavior

SCAN CELL

functional path: D ------> Q
                       ^
scan path: SI -> mux --|
               |
             SE=1 (shift), SE=0 (functional)

Shift mode exposes internal state through SI/SO.

Root-cause narrative

ROOT-CAUSE TREE - Scan Cell Architecture

scan cell legality rate, scan replacement ratio, scan DRC count regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Scan insertion replaces functional flops with scan-capable cells so internal state becomes controllable and observable in test mode.

Metric: scan cell legality rate, scan replacement ratio, scan DRC count