Scan Cell Architecture: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for Scan Cell Architecture focuses on scan cell legality rate, scan replacement ratio, scan DRC count. The goal is to convert metric movement into mechanism, owner, and release decision.

Treat these as a release contract. Ambiguity here creates expensive debug loops because teams optimize against different assumptions.

INPUTS
  - scan/ATPG architecture and constraints
  - fault model and quality target policy
  - pattern generation config + tester limits
  - timing/power/physical assumptions

OUTPUTS
  - quality metrics and closure status
  - signed artifacts and owner approvals
  - diagnosis evidence for residual risk
  - release, waiver, or escalation decision

Flow sequence

DFT FLOW - Scan Cell Architecture

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: scan cell legality rate, scan replacement ratio, scan DRC count

Ownership map

OWNERSHIP MAP - Scan Cell Architecture

artifact              owner
----------------      -----------------
architecture/report DFT owner
constraints/setup   RTL owner
physical/test       synthesis owner

Name an owner for each failing metric cluster.

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Scan insertion replaces functional flops with scan-capable cells so internal state becomes controllable and observable in test mode.

Metric: scan cell legality rate, scan replacement ratio, scan DRC count