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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
    • Scan Cell Architecture
      • Scan Cell Architecture: Mechanism
      • Scan Cell Architecture: Inputs & Outputs
      • Scan Cell Architecture: Reports & Metrics
      • Scan Cell Architecture: Debug Playbook
      • Scan Cell Architecture: Worked Example
      • Scan Cell Architecture: Pitfalls & Red Flags
      • Scan Cell Architecture: Interview Drills
      • Scan Cell Architecture: Review Checklist
      • Scan Cell Architecture: Theory Deep Dive
      • Scan Cell Architecture: Design Space
      • Scan Cell Architecture: Expanded Case Study
      • Scan Cell Architecture: Step-by-Step Walkthrough
      • Scan Cell Architecture: Comparison Matrix
      • Scan Cell Architecture: Software / Programmer View
      • Scan Cell Architecture: Silicon PPA Impact
    • Chain Stitching Rules
    • Clocking for Test
    • Scan-Ready RTL
    • Scan Fundamentals: Tricky Q&A
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Scan Cell Architecture
  1. Topics
  2. Design for Test
  3. Scan Fundamentals
  4. Scan Cell Architecture
  5. Scan Cell Architecture: Review Checklist

DFT / ATPG · All levels

Scan Cell Architecture: Review Checklist

Review Checklist for Scan Cell Architecture.

On this page

    Review checklist

    Review Checklist for Scan Cell Architecture focuses on scan cell legality rate, scan replacement ratio, scan DRC count. The goal is to convert metric movement into mechanism, owner, and release decision.

    • Run tags and scenario context are explicit.

    • Constraints and legality assumptions are documented.

    • Quality, timing, and test-power checks are included.

    • Diagnosis evidence supports residual-risk decision.

    • Owners signed: DFT owner, RTL owner, synthesis owner.

    Signoff ownership

    Diagram
    OWNERSHIP MAP - Scan Cell Architecture
    
    artifact              owner
    ----------------      -----------------
    architecture/report DFT owner
    constraints/setup   RTL owner
    physical/test       synthesis owner
    
    Name an owner for each failing metric cluster.

    DFT deep dive

    Scan architecture quality determines whether ATPG can control and observe real silicon state.

    Concept diagram

    Diagram
    SCAN INSERTION FLOW
    
    scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

    Metric graph

    Diagram
    CHAIN BALANCE
    
    chain length spread
    low spread   = better shift time
    high spread  = routing + hold risk

    Reports and artifacts

    • scan insertion summary

    • chain balance report

    • scan DRC log

    • clocking legality report

    Mini case study

    Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

    Debug branches

    • Check scan replacement first

    • Audit chain legality by domain

    • Validate shift/capture clocks

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Scan insertion replaces functional flops with scan-capable cells so internal state becomes controllable and observable in test mode.

    Metric: scan cell legality rate, scan replacement ratio, scan DRC count

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    See also

    • Scan Cell Architecture: Mechanism
    • Scan Cell Architecture: Inputs & Outputs
    • Scan Cell Architecture: Reports & Metrics