Physical DFT Debug: Worked Example

Worked example

Worked Example for Physical DFT Debug focuses on physical root-cause turnaround, repeat DFT route violations, signoff escape risk. The goal is to convert metric movement into mechanism, owner, and release decision.

A release review shows regression on physical root-cause turnaround, repeat DFT route violations, signoff escape risk. The strongest first move is to freeze evidence, isolate one failing bucket, and prove mechanism before changing flow knobs.

Sequence under inspection

DFT FLOW - Physical DFT Debug

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: physical root-cause turnaround, repeat DFT route violations, signoff escape risk

Physical DFT flow

chain planning -> floorplan -> route/timing debug -> closure

1. Capture failing report and exact run tags.

2. Tag scenario (mode, lot/corner, pattern class).

3. Trace first dependency that changed.

4. Compare against physical debug log, failing path snapshots, fix validation report.

5. Choose one reversible fix and predefine regression checks.

Did the fix work?

BEFORE / AFTER - Physical DFT Debug

metric quality
  ^
  |                    --- release target
  |      o regressed
  |           o baseline
  |                o after fix
  +-------------------------------> closure iteration

Prove quality, timing, and test-power all moved safely.

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Physical DFT debug traces violations to chain ordering, buffering strategy, clock topology, or extraction/view mismatches.

Metric: physical root-cause turnaround, repeat DFT route violations, signoff escape risk