Pitfalls and red flags

Pitfalls & Red Flags for Physical DFT Debug focuses on physical root-cause turnaround, repeat DFT route violations, signoff escape risk. The goal is to convert metric movement into mechanism, owner, and release decision.

• Coverage improves while diagnosis quality degrades.

• Pattern count drops but test escapes rise.

• Shift timing passes while capture timing regresses.

• Power fixes alter quality behavior without retest.

• Owner handoff is unclear for recurring failures.

Layer responsibility check

DFT OWNERSHIP LAYERS - Physical DFT Debug

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Physical DFT debug traces violations to chain ordering, buffering strategy, clock topology, or extraction/view mismatches.

Metric: physical root-cause turnaround, repeat DFT route violations, signoff escape risk