DFT / ATPG · All levels

Physical DFT Debug: Comparison Matrix

Comparison Matrix for Physical DFT Debug.

Comparison matrix

Chain order and placement strategy trade congestion and closure time.

diagram

+------------------+----------------+----------------+----------------+
| Approach         | Strength       | Weakness       | Best when      |
+------------------+----------------+----------------+----------------+
| Conservative     | safe           | higher cost    | ramp-sensitive |
| Balanced         | practical      | needs rigor    | production     |
| Aggressive       | fast           | escape risk    | schedule pressure |
| Architecture     | durable        | slow           | repeated pain  |
+------------------+----------------+----------------+----------------+

When to choose each approach

Tie approach to product risk and tester constraints

Interview traps

Optimizing one metric only
No regression ownership

Evidence comparison

diagram

DFT EVIDENCE MATRIX - Physical DFT Debug

+-------------------+------------------------+--------------------------+-------------------------+
| Evidence           | Tells you              | Does not prove           | Next action             |
+-------------------+------------------------+--------------------------+-------------------------+
| coverage report    | fault detect trends    | silicon root cause       | inspect bucket details  |
| pattern diff       | generation changes     | architecture quality     | replay suspect patterns |
| timing/power report| test closure margin    | diagnosis confidence     | correlate fail logs     |
| diagnosis summary  | likely defect classes  | ownership decision       | assign action owner     |
| signoff checklist  | process completeness   | correctness of evidence  | peer review artifacts   |
+-------------------+------------------------+--------------------------+-------------------------+

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

diagram

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

scan physical wirelength
congestion heatmap
test clock skew
handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

Correlate chain order with congestion
Place compression logic near chain clusters
Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.

Common pitfalls

Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.

Principal DFT review addendum

Physical DFT debug traces violations to chain ordering, buffering strategy, clock topology, or extraction/view mismatches.

Metric: physical root-cause turnaround, repeat DFT route violations, signoff escape risk

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