Test Logic Floorplan turns DFT intent into measurable release confidence. Placement of decompressors, compactors, and BIST controllers impacts routing quality, clocking, and timing closure effort. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.
When compression logic placement quality, test route detours, floorplan DFT ECO count moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?
DFT CLOSURE FLOW - Test Logic Floorplan
scan/test architecture
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ATPG constraints + fault models
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pattern generation + compression
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timing/power/physical validation
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silicon diagnosis and release signoff
Debug rule: always state metric, run tags, and owning team with any claim.Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.
decompressor/compactor placement too far from chains
-> detours + skew + route pressureDFT FLOW - Test Logic Floorplan
scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
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controllability shift balance channel use coverage silicon correlation
Primary metric: compression logic placement quality, test route detours, floorplan DFT ECO countDFT OWNERSHIP LAYERS - Test Logic Floorplan
layer owns failure mode
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rtl/architecture scanability hooks uncontrollable logic
atpg/constraints legal pattern intent aborts, low coverage
physical/clocking chain route + test clocks shift hold/timing escapes
tester/program pattern apply integrity false binning / bad fails
quality signoff release criteria escapes or schedule slipPrimary metric: compression logic placement quality, test route detours, floorplan DFT ECO count.
Primary artifact: test logic floorplan review, placement snapshots, routing detour report.
Owners to bring into review: PD owner, DFT owner, CTS owner.
One failing signature and one reduced reproduction path.
Exact run tags for constraints, patterns, and tester program.
OWNERSHIP MAP - Test Logic Floorplan
artifact owner
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architecture/report PD owner
constraints/setup DFT owner
physical/test CTS owner
Name an owner for each failing metric cluster.Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.
State metric and run tags with every claim.
Connect every fix to a regression matrix.
Treat quality, timing, and power as coupled.
Coverage-centric decisions without legality checks.
Pattern changes without tester correlation.
Release calls without owner signoff.
Physical integration quality decides whether DFT architecture survives implementation realities.
PHYSICAL DFT FLOW
chain planning -> floorplan placement -> route -> test timing/power validationROUTING BURDEN
poor chain order -> longer routes -> more hold buffersscan physical wirelength
congestion heatmap
test clock skew
handoff issue tracker
Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.
Correlate chain order with congestion
Place compression logic near chain clusters
Keep DFT-PD handoff versioned
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.