Test Logic Floorplan: Theory Deep Dive

Foundational theory

Test Logic Floorplan is central to DFT Physical Integration. Placement of decompressors, compactors, and BIST controllers impacts routing quality, clocking, and timing closure effort. Senior DFT engineers tie metric movement to architecture assumptions, constraints, and silicon evidence rather than isolated tool output.

Core concepts explained

• Placement of decompressors, compactors, and BIST controllers impacts routing quality, clocking, and timing closure effort.

• Primary metric: compression logic placement quality, test route detours, floorplan DFT ECO count

• Primary artifact: test logic floorplan review, placement snapshots, routing detour report

• Owners: PD owner, DFT owner, CTS owner

• Controllability and observability must be explicit

• Production-quality requires reproducible pattern and tester tags

Why this matters at release

At release, Test Logic Floorplan issues can create coverage escapes, unstable production bins, or long debug loops. Physical implementation decides whether DFT architecture remains feasible at scale.

Mental model

decompressor/compactor placement too far from chains
  -> detours + skew + route pressure

Worked intuition

1. Name failing metric and scenario context (mode, lot/corner, program).

2. Open compression logic placement quality, test route detours, floorplan DFT ECO count trend and isolate dominant failing bucket.

3. Trace architecture assumptions and legality constraints.

4. Check compression, clocking, and unknown handling dependencies.

5. Collect test logic floorplan review, placement snapshots, routing detour report and confirm run tags.

6. Classify issue: model/constraint, physical/test setup, or real defect signal.

7. Propose minimal fix and list timing/power/quality regression checks.

Common misconceptions

• Coverage percent alone proves release readiness.

• More compression always means better outcome.

• Silicon mismatch can be debugged without pattern/tester traceability.

• Shift timing and test power can be signed independently.

Visual reinforcement

Compression logic placement

decompressor/compactor placement too far from chains
  -> detours + skew + route pressure

Layer responsibilities

DFT OWNERSHIP LAYERS - Test Logic Floorplan

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Theory reinforcement

Physical implementation decides whether DFT architecture remains feasible at scale.