Test Logic Floorplan: Step-by-Step Walkthrough

Step-by-step analysis walkthrough

Use when you own Test Logic Floorplan in a DFT closure review.

1. Open release criteria and failing metric dashboard.

2. Partition failures by pattern family and operating context.

3. Inspect constraints, clocks, masks, and unknown handling.

4. Check architecture assumptions against implementation reality.

5. Review diagnosis evidence for repeatability.

6. Assign owner and propose smallest high-confidence change.

7. Run timing, power, and quality regressions.

8. Capture final signoff or waiver decision.

Artifacts to collect

• test logic floorplan review, placement snapshots, routing detour report

• pattern tag manifest

• tester program revision

• signoff checklist

• owner tracker

Decision memo template

DFT DECISION MEMO - Test Logic Floorplan
scenario:
metric:
hypothesis:
fix:
regression:
owners: PD owner, DFT owner, CTS owner

Reference visuals

Compression logic placement

decompressor/compactor placement too far from chains
  -> detours + skew + route pressure

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Placement of decompressors, compactors, and BIST controllers impacts routing quality, clocking, and timing closure effort.

Metric: compression logic placement quality, test route detours, floorplan DFT ECO count