Test Logic Floorplan: Worked Example

Worked example

Worked Example for Test Logic Floorplan focuses on compression logic placement quality, test route detours, floorplan DFT ECO count. The goal is to convert metric movement into mechanism, owner, and release decision.

A release review shows regression on compression logic placement quality, test route detours, floorplan DFT ECO count. The strongest first move is to freeze evidence, isolate one failing bucket, and prove mechanism before changing flow knobs.

Sequence under inspection

DFT FLOW - Test Logic Floorplan

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: compression logic placement quality, test route detours, floorplan DFT ECO count

Compression logic placement

decompressor/compactor placement too far from chains
  -> detours + skew + route pressure

1. Capture failing report and exact run tags.

2. Tag scenario (mode, lot/corner, pattern class).

3. Trace first dependency that changed.

4. Compare against test logic floorplan review, placement snapshots, routing detour report.

5. Choose one reversible fix and predefine regression checks.

Did the fix work?

BEFORE / AFTER - Test Logic Floorplan

metric quality
  ^
  |                    --- release target
  |      o regressed
  |           o baseline
  |                o after fix
  +-------------------------------> closure iteration

Prove quality, timing, and test-power all moved safely.

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Placement of decompressors, compactors, and BIST controllers impacts routing quality, clocking, and timing closure effort.

Metric: compression logic placement quality, test route detours, floorplan DFT ECO count