Test Logic Floorplan: Interview Drills

Interview drills

Interview Drills for Test Logic Floorplan focuses on compression logic placement quality, test route detours, floorplan DFT ECO count. The goal is to convert metric movement into mechanism, owner, and release decision.

PROMPT
You observe compression logic placement quality, test route detours, floorplan DFT ECO count on Test Logic Floorplan. Walk through diagnosis and release decision.

STRONG ANSWER
1. States context and run tags.
2. Explains mechanism: Placement of decompressors, compactors, and BIST controllers impacts routing quality, clocking, and timing closure effort.
3. Requests test logic floorplan review, placement snapshots, routing detour report.
4. Proposes minimal fix and regression.

WEAK ANSWER
Jumps to tool switches without evidence quality, ownership, or regression plan.

Diagram to draw on the whiteboard

Compression logic placement

decompressor/compactor placement too far from chains
  -> detours + skew + route pressure

Root-cause narrative

ROOT-CAUSE TREE - Test Logic Floorplan

compression logic placement quality, test route detours, floorplan DFT ECO count regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Placement of decompressors, compactors, and BIST controllers impacts routing quality, clocking, and timing closure effort.

Metric: compression logic placement quality, test route detours, floorplan DFT ECO count