Test Logic Floorplan: Reports & Metrics

Reports and metrics

Reports & Metrics for Test Logic Floorplan focuses on compression logic placement quality, test route detours, floorplan DFT ECO count. The goal is to convert metric movement into mechanism, owner, and release decision.

A report should support a release decision for compression logic placement quality, test route detours, floorplan DFT ECO count. One headline number is rarely enough without setup tags and bucket-level evidence.

Metric movement

METRIC GRAPH - compression logic placement quality, test route detours, floorplan DFT ECO count

quality metric
  ^
  |                         target
  |                       - - - - - - -
  |                  o after fix + regression
  |              o
  |         o baseline
  |    o regressed run
  +--------------------------------------> closure iteration
    input audit     focused fix      signoff review

Readout:
  - explain what moved, why it moved, and who approved it

Distribution view

PATTERN HISTOGRAM - Test Logic Floorplan

pattern count
  |      ***
  |    *******
  |  ***********
  |*************  <- high-volume tail (optimize here)
  +--------------------> pattern buckets
   smoke  stuck-at  transition  diagnosis

Balance quality and tester limits together.

• Track compression logic placement quality, test route detours, floorplan DFT ECO count by context and pattern class.

• Review trend and bucket detail together.

• Keep quality, timing, and power metrics in one dashboard.

• Store each metric next to the artifact and run tag.

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Reading reports