Test Logic Floorplan: Expanded Case Study

Extended case study

Release review: compression logic placement quality, test route detours, floorplan DFT ECO count regresses after a test-flow update touching Test Logic Floorplan.

Background

Team had prior signoff, then a new program/config introduced regressions in selected buckets.

Symptoms observed

• compression logic placement quality, test route detours, floorplan DFT ECO count regression

• Mismatch between simulation and tester

• Escalation without clear owner

Investigation timeline

1. Hour 0: freeze pattern set, constraints, and tester program tags

2. Hour 1: isolate first failing bucket by mode/lot

3. Hour 2: verify legality and constraints assumptions

4. Hour 3: correlate with physical/timing/power context

5. Hour 4: choose minimal reversible fix

6. Hour 5: run full signoff regression matrix

7. Hour 6: publish decision memo and owners

Root cause

Root cause tied to Test Logic Floorplan: Placement of decompressors, compactors, and BIST controllers impacts routing quality, clocking, and timing closure effort.

Fix and validation

• Apply bounded fix with owner

• Re-run test logic floorplan review, placement snapshots, routing detour report

• Re-validate quality, timing, and test power

Lessons learned

• Tag every run artifact

• Mechanism first, command second

• Close with explicit release decision

CASE STUDY - Test Logic Floorplan
baseline metric / regressed metric / post-fix metric

Sequence under stress

DFT FLOW - Test Logic Floorplan

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: compression logic placement quality, test route detours, floorplan DFT ECO count

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Placement of decompressors, compactors, and BIST controllers impacts routing quality, clocking, and timing closure effort.

Metric: compression logic placement quality, test route detours, floorplan DFT ECO count