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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
    • Scan Chain Physical Effects
    • Test Logic Floorplan
    • DFT-PD Handoff
    • Physical DFT Debug
      • Physical DFT Debug: Mechanism
      • Physical DFT Debug: Inputs & Outputs
      • Physical DFT Debug: Reports & Metrics
      • Physical DFT Debug: Debug Playbook
      • Physical DFT Debug: Worked Example
      • Physical DFT Debug: Pitfalls & Red Flags
      • Physical DFT Debug: Interview Drills
      • Physical DFT Debug: Review Checklist
      • Physical DFT Debug: Theory Deep Dive
      • Physical DFT Debug: Design Space
      • Physical DFT Debug: Expanded Case Study
      • Physical DFT Debug: Step-by-Step Walkthrough
      • Physical DFT Debug: Comparison Matrix
      • Physical DFT Debug: Software / Programmer View
      • Physical DFT Debug: Silicon PPA Impact
    • DFT Physical Integration: Tricky Q&A
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Physical DFT Debug
  1. Topics
  2. Design for Test
  3. DFT Physical Integration
  4. Physical DFT Debug
  5. Physical DFT Debug: Reports & Metrics

DFT / ATPG · All levels

Physical DFT Debug: Reports & Metrics

Reports & Metrics for Physical DFT Debug.

On this page

    Reports and metrics

    Reports & Metrics for Physical DFT Debug focuses on physical root-cause turnaround, repeat DFT route violations, signoff escape risk. The goal is to convert metric movement into mechanism, owner, and release decision.

    A report should support a release decision for physical root-cause turnaround, repeat DFT route violations, signoff escape risk. One headline number is rarely enough without setup tags and bucket-level evidence.

    Metric movement

    Diagram
    METRIC GRAPH - physical root-cause turnaround, repeat DFT route violations, signoff escape risk
    
    quality metric
      ^
      |                         target
      |                       - - - - - - -
      |                  o after fix + regression
      |              o
      |         o baseline
      |    o regressed run
      +--------------------------------------> closure iteration
        input audit     focused fix      signoff review
    
    Readout:
      - explain what moved, why it moved, and who approved it

    Distribution view

    Diagram
    PATTERN HISTOGRAM - Physical DFT Debug
    
    pattern count
      |      ***
      |    *******
      |  ***********
      |*************  <- high-volume tail (optimize here)
      +--------------------> pattern buckets
       smoke  stuck-at  transition  diagnosis
    
    Balance quality and tester limits together.
    • Track physical root-cause turnaround, repeat DFT route violations, signoff escape risk by context and pattern class.

    • Review trend and bucket detail together.

    • Keep quality, timing, and power metrics in one dashboard.

    • Store each metric next to the artifact and run tag.

    DFT deep dive

    Physical integration quality decides whether DFT architecture survives implementation realities.

    Concept diagram

    Diagram
    PHYSICAL DFT FLOW
    
    chain planning -> floorplan placement -> route -> test timing/power validation

    Metric graph

    Diagram
    ROUTING BURDEN
    
    poor chain order -> longer routes -> more hold buffers

    Reports and artifacts

    • scan physical wirelength

    • congestion heatmap

    • test clock skew

    • handoff issue tracker

    Mini case study

    Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

    Debug branches

    • Correlate chain order with congestion

    • Place compression logic near chain clusters

    • Keep DFT-PD handoff versioned

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Reading reports

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    Next: Physical DFT Debug: Debug Playbook

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    See also

    • Physical DFT Debug: Mechanism
    • Physical DFT Debug: Worked Example
    • Physical DFT Debug: Pitfalls & Red Flags