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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
    • MBIST Integration
    • Memory Repair Flow
    • LBIST Overview
      • LBIST Overview: Mechanism
      • LBIST Overview: Inputs & Outputs
      • LBIST Overview: Reports & Metrics
      • LBIST Overview: Debug Playbook
      • LBIST Overview: Worked Example
      • LBIST Overview: Pitfalls & Red Flags
      • LBIST Overview: Interview Drills
      • LBIST Overview: Review Checklist
      • LBIST Overview: Theory Deep Dive
      • LBIST Overview: Design Space
      • LBIST Overview: Expanded Case Study
      • LBIST Overview: Step-by-Step Walkthrough
      • LBIST Overview: Comparison Matrix
      • LBIST Overview: Software / Programmer View
      • LBIST Overview: Silicon PPA Impact
    • BIST Signoff
    • MBIST & LBIST: Tricky Q&A
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹LBIST Overview
  1. Topics
  2. Design for Test
  3. MBIST & LBIST
  4. LBIST Overview
  5. LBIST Overview: Debug Playbook

DFT / ATPG · All levels

LBIST Overview: Debug Playbook

Debug Playbook for LBIST Overview.

On this page

    Debug playbook

    Debug Playbook for LBIST Overview focuses on LBIST signature quality, random-pattern-resistant fault count, runtime budget. The goal is to convert metric movement into mechanism, owner, and release decision.

    Debug aims to find the first incorrect assumption, not the loudest downstream symptom. Start with reproducibility and ownership.

    Root-cause tree

    Diagram
    ROOT-CAUSE TREE - LBIST Overview
    
    LBIST signature quality, random-pattern-resistant fault count, runtime budget regresses
            |
      setup changed?
        /        \
      yes         no
      |            |
    constraint    silicon or
    or ATPG       physical/test path
     /    \          |
    SDC   model    chain/clock/power/diagnosis
    diff  diff     isolate first failing signature
    1. Freeze run tags for patterns, constraints, and tester setup.

    2. Isolate first failing metric bucket and scenario.

    3. Classify failure source: model, constraints, physical, or silicon.

    4. Prove mechanism with one reduced replay or targeted run.

    5. Apply smallest owner-controlled fix.

    6. Re-run timing, power, and quality regression matrix.

    Review memo template

    Diagram
    STAFF DFT REVIEW MEMO - MBIST & LBIST / LBIST Overview
    
    1. Symptom
       - Watched metric: LBIST signature quality, random-pattern-resistant fault count, runtime budget
       - Failing scenario: <mode/lot/corner/program>
       - Pattern class: <scan/transition/compressed/BIST/JTAG>
       - Tags: <constraints, patterns, tester program, netlist>
    
    2. Mechanism hypothesis
       - Primary mechanism: LBIST uses on-chip pattern generation and signature compression for in-system logic test where external ATPG access is limited.
       - Competing hypothesis: <constraint issue, model issue, physical issue, silicon issue>
       - Missing evidence: <report, replay, diagnosis trace>
    
    3. Proposed action
       - Minimal reversible change: <constraint fix, architecture tweak, pattern update>
       - Expected metric movement: <delta>
       - Regression risk: timing, power, quality, schedule
    
    4. Signoff
       - Re-run artifact: LBIST architecture doc, MISR signature report, resistant fault list
       - Required owners: DFT architect, safety owner, product engineering owner
       - Final decision: release, waive, rollback, or escalate

    DFT deep dive

    BIST value is realized only when insertion, diagnosis, and repair are tied to production flow.

    Concept diagram

    Diagram
    BIST FLOW
    
    insert MBIST/LBIST -> execute -> collect signatures -> diagnose/repair -> signoff

    Metric graph

    Diagram
    REPAIR EFFECT
    
    yield
      ^
      |      o pre-repair
      |             o post-repair
      +---------------------> lot

    Reports and artifacts

    • MBIST insertion coverage

    • repair signature report

    • LBIST resistant fault list

    • BIST release checklist

    Mini case study

    Fuse programming mismatch blocked repair activation; corrected bring-up script recovered expected yield uplift.

    Debug branches

    • Validate BIST reachability

    • Correlate fail maps to repair signatures

    • Audit in-field boot test budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    LBIST uses on-chip pattern generation and signature compression for in-system logic test where external ATPG access is limited.

    Metric: LBIST signature quality, random-pattern-resistant fault count, runtime budget

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    See also

    • LBIST Overview: Mechanism
    • LBIST Overview: Inputs & Outputs
    • LBIST Overview: Pitfalls & Red Flags