Memory Repair Flow

What this topic teaches

Memory Repair Flow turns DFT intent into measurable release confidence. Redundancy analysis maps diagnosed memory defects to spare rows/columns, trading area overhead for yield recovery. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.

The senior-engineer question

When repairable fail ratio, spare utilization, post-repair yield uplift moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?

DFT CLOSURE FLOW - Memory Repair Flow

scan/test architecture
        |
        v
ATPG constraints + fault models
        |
        v
pattern generation + compression
        |
        v
timing/power/physical validation
        |
        v
silicon diagnosis and release signoff

Debug rule: always state metric, run tags, and owning team with any claim.

Picture the closure flow

Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.

Repair flow

BIST fail bitmap -> redundancy analysis -> spare assignment -> fuse programming -> retest

Process sequence

DFT FLOW - Memory Repair Flow

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: repairable fail ratio, spare utilization, post-repair yield uplift

Ownership layers

DFT OWNERSHIP LAYERS - Memory Repair Flow

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

Evidence to collect

• Primary metric: repairable fail ratio, spare utilization, post-repair yield uplift.

• Primary artifact: BIRA/BISR report, repair signature table, redundancy summary.

• Owners to bring into review: memory test owner, yield owner, DFT lead.

• One failing signature and one reduced reproduction path.

• Exact run tags for constraints, patterns, and tester program.

Ownership map

OWNERSHIP MAP - Memory Repair Flow

artifact              owner
----------------      -----------------
architecture/report memory test owner
constraints/setup   yield owner
physical/test       DFT lead

Name an owner for each failing metric cluster.

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

• State metric and run tags with every claim.

• Connect every fix to a regression matrix.

• Treat quality, timing, and power as coupled.

Common pitfalls

• Coverage-centric decisions without legality checks.

• Pattern changes without tester correlation.

• Release calls without owner signoff.

DFT deep dive

BIST value is realized only when insertion, diagnosis, and repair are tied to production flow.

Concept diagram

BIST FLOW

insert MBIST/LBIST -> execute -> collect signatures -> diagnose/repair -> signoff

Metric graph

REPAIR EFFECT

yield
  ^
  |      o pre-repair
  |             o post-repair
  +---------------------> lot

Reports and artifacts

• MBIST insertion coverage

• repair signature report

• LBIST resistant fault list

• BIST release checklist

Mini case study

Fuse programming mismatch blocked repair activation; corrected bring-up script recovered expected yield uplift.

Debug branches

• Validate BIST reachability

• Correlate fail maps to repair signatures

• Audit in-field boot test budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.