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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
    • MBIST Integration
    • Memory Repair Flow
      • Memory Repair Flow: Mechanism
      • Memory Repair Flow: Inputs & Outputs
      • Memory Repair Flow: Reports & Metrics
      • Memory Repair Flow: Debug Playbook
      • Memory Repair Flow: Worked Example
      • Memory Repair Flow: Pitfalls & Red Flags
      • Memory Repair Flow: Interview Drills
      • Memory Repair Flow: Review Checklist
      • Memory Repair Flow: Theory Deep Dive
      • Memory Repair Flow: Design Space
      • Memory Repair Flow: Expanded Case Study
      • Memory Repair Flow: Step-by-Step Walkthrough
      • Memory Repair Flow: Comparison Matrix
      • Memory Repair Flow: Software / Programmer View
      • Memory Repair Flow: Silicon PPA Impact
    • LBIST Overview
    • BIST Signoff
    • MBIST & LBIST: Tricky Q&A
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Memory Repair Flow
  1. Topics
  2. Design for Test
  3. MBIST & LBIST
  4. Memory Repair Flow
  5. Memory Repair Flow: Worked Example

DFT / ATPG · All levels

Memory Repair Flow: Worked Example

Worked Example for Memory Repair Flow.

On this page

    Worked example

    Worked Example for Memory Repair Flow focuses on repairable fail ratio, spare utilization, post-repair yield uplift. The goal is to convert metric movement into mechanism, owner, and release decision.

    A release review shows regression on repairable fail ratio, spare utilization, post-repair yield uplift. The strongest first move is to freeze evidence, isolate one failing bucket, and prove mechanism before changing flow knobs.

    Sequence under inspection

    Diagram
    DFT FLOW - Memory Repair Flow
    
    scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
          |                |                |            |             |
     controllability   shift balance    channel use   coverage     silicon correlation
    
    Primary metric: repairable fail ratio, spare utilization, post-repair yield uplift

    Repair flow

    Diagram
    BIST fail bitmap -> redundancy analysis -> spare assignment -> fuse programming -> retest
    1. Capture failing report and exact run tags.

    2. Tag scenario (mode, lot/corner, pattern class).

    3. Trace first dependency that changed.

    4. Compare against BIRA/BISR report, repair signature table, redundancy summary.

    5. Choose one reversible fix and predefine regression checks.

    Did the fix work?

    Diagram
    BEFORE / AFTER - Memory Repair Flow
    
    metric quality
      ^
      |                    --- release target
      |      o regressed
      |           o baseline
      |                o after fix
      +-------------------------------> closure iteration
    
    Prove quality, timing, and test-power all moved safely.

    DFT deep dive

    BIST value is realized only when insertion, diagnosis, and repair are tied to production flow.

    Concept diagram

    Diagram
    BIST FLOW
    
    insert MBIST/LBIST -> execute -> collect signatures -> diagnose/repair -> signoff

    Metric graph

    Diagram
    REPAIR EFFECT
    
    yield
      ^
      |      o pre-repair
      |             o post-repair
      +---------------------> lot

    Reports and artifacts

    • MBIST insertion coverage

    • repair signature report

    • LBIST resistant fault list

    • BIST release checklist

    Mini case study

    Fuse programming mismatch blocked repair activation; corrected bring-up script recovered expected yield uplift.

    Debug branches

    • Validate BIST reachability

    • Correlate fail maps to repair signatures

    • Audit in-field boot test budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Redundancy analysis maps diagnosed memory defects to spare rows/columns, trading area overhead for yield recovery.

    Metric: repairable fail ratio, spare utilization, post-repair yield uplift

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    See also

    • Memory Repair Flow: Mechanism
    • Memory Repair Flow: Inputs & Outputs
    • Memory Repair Flow: Reports & Metrics