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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
    • MBIST Integration
    • Memory Repair Flow
      • Memory Repair Flow: Mechanism
      • Memory Repair Flow: Inputs & Outputs
      • Memory Repair Flow: Reports & Metrics
      • Memory Repair Flow: Debug Playbook
      • Memory Repair Flow: Worked Example
      • Memory Repair Flow: Pitfalls & Red Flags
      • Memory Repair Flow: Interview Drills
      • Memory Repair Flow: Review Checklist
      • Memory Repair Flow: Theory Deep Dive
      • Memory Repair Flow: Design Space
      • Memory Repair Flow: Expanded Case Study
      • Memory Repair Flow: Step-by-Step Walkthrough
      • Memory Repair Flow: Comparison Matrix
      • Memory Repair Flow: Software / Programmer View
      • Memory Repair Flow: Silicon PPA Impact
    • LBIST Overview
    • BIST Signoff
    • MBIST & LBIST: Tricky Q&A
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Memory Repair Flow
  1. Topics
  2. Design for Test
  3. MBIST & LBIST
  4. Memory Repair Flow
  5. Memory Repair Flow: Review Checklist

DFT / ATPG · All levels

Memory Repair Flow: Review Checklist

Review Checklist for Memory Repair Flow.

On this page

    Review checklist

    Review Checklist for Memory Repair Flow focuses on repairable fail ratio, spare utilization, post-repair yield uplift. The goal is to convert metric movement into mechanism, owner, and release decision.

    • Run tags and scenario context are explicit.

    • Constraints and legality assumptions are documented.

    • Quality, timing, and test-power checks are included.

    • Diagnosis evidence supports residual-risk decision.

    • Owners signed: memory test owner, yield owner, DFT lead.

    Signoff ownership

    Diagram
    OWNERSHIP MAP - Memory Repair Flow
    
    artifact              owner
    ----------------      -----------------
    architecture/report memory test owner
    constraints/setup   yield owner
    physical/test       DFT lead
    
    Name an owner for each failing metric cluster.

    DFT deep dive

    BIST value is realized only when insertion, diagnosis, and repair are tied to production flow.

    Concept diagram

    Diagram
    BIST FLOW
    
    insert MBIST/LBIST -> execute -> collect signatures -> diagnose/repair -> signoff

    Metric graph

    Diagram
    REPAIR EFFECT
    
    yield
      ^
      |      o pre-repair
      |             o post-repair
      +---------------------> lot

    Reports and artifacts

    • MBIST insertion coverage

    • repair signature report

    • LBIST resistant fault list

    • BIST release checklist

    Mini case study

    Fuse programming mismatch blocked repair activation; corrected bring-up script recovered expected yield uplift.

    Debug branches

    • Validate BIST reachability

    • Correlate fail maps to repair signatures

    • Audit in-field boot test budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Redundancy analysis maps diagnosed memory defects to spare rows/columns, trading area overhead for yield recovery.

    Metric: repairable fail ratio, spare utilization, post-repair yield uplift

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    See also

    • Memory Repair Flow: Mechanism
    • Memory Repair Flow: Inputs & Outputs
    • Memory Repair Flow: Reports & Metrics