Memory Repair Flow: Software / Programmer View

RTL / integration view

Memory wrappers and test access points must be planned in design stage.

What teams feel

• Unexpected untestables

• clock/reset test-mode conflicts

RTL structure impact

• Scan hooks

• mode controls

• debug access gating

Tool interaction

• Synthesis transforms affecting scan paths

• clock-gating interaction

Mitigations

• DFT lint gates

• test-aware coding standards

• joint RTL/DFT reviews

RTL VIEW - Memory Repair Flow
// mode logic changed -> recheck controllability and constraints

Layer touch points

DFT OWNERSHIP LAYERS - Memory Repair Flow

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

BIST value is realized only when insertion, diagnosis, and repair are tied to production flow.

Concept diagram

BIST FLOW

insert MBIST/LBIST -> execute -> collect signatures -> diagnose/repair -> signoff

Metric graph

REPAIR EFFECT

yield
  ^
  |      o pre-repair
  |             o post-repair
  +---------------------> lot

Reports and artifacts

• MBIST insertion coverage

• repair signature report

• LBIST resistant fault list

• BIST release checklist

Mini case study

Fuse programming mismatch blocked repair activation; corrected bring-up script recovered expected yield uplift.

Debug branches

• Validate BIST reachability

• Correlate fail maps to repair signatures

• Audit in-field boot test budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Redundancy analysis maps diagnosed memory defects to spare rows/columns, trading area overhead for yield recovery.

Metric: repairable fail ratio, spare utilization, post-repair yield uplift