Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
    • MBIST Integration
    • Memory Repair Flow
      • Memory Repair Flow: Mechanism
      • Memory Repair Flow: Inputs & Outputs
      • Memory Repair Flow: Reports & Metrics
      • Memory Repair Flow: Debug Playbook
      • Memory Repair Flow: Worked Example
      • Memory Repair Flow: Pitfalls & Red Flags
      • Memory Repair Flow: Interview Drills
      • Memory Repair Flow: Review Checklist
      • Memory Repair Flow: Theory Deep Dive
      • Memory Repair Flow: Design Space
      • Memory Repair Flow: Expanded Case Study
      • Memory Repair Flow: Step-by-Step Walkthrough
      • Memory Repair Flow: Comparison Matrix
      • Memory Repair Flow: Software / Programmer View
      • Memory Repair Flow: Silicon PPA Impact
    • LBIST Overview
    • BIST Signoff
    • MBIST & LBIST: Tricky Q&A
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
Loading lesson

‹Memory Repair Flow
  1. Topics
  2. Design for Test
  3. MBIST & LBIST
  4. Memory Repair Flow
  5. Memory Repair Flow: Debug Playbook

DFT / ATPG · All levels

Memory Repair Flow: Debug Playbook

Debug Playbook for Memory Repair Flow.

On this page

    Debug playbook

    Debug Playbook for Memory Repair Flow focuses on repairable fail ratio, spare utilization, post-repair yield uplift. The goal is to convert metric movement into mechanism, owner, and release decision.

    Debug aims to find the first incorrect assumption, not the loudest downstream symptom. Start with reproducibility and ownership.

    Root-cause tree

    Diagram
    ROOT-CAUSE TREE - Memory Repair Flow
    
    repairable fail ratio, spare utilization, post-repair yield uplift regresses
            |
      setup changed?
        /        \
      yes         no
      |            |
    constraint    silicon or
    or ATPG       physical/test path
     /    \          |
    SDC   model    chain/clock/power/diagnosis
    diff  diff     isolate first failing signature
    1. Freeze run tags for patterns, constraints, and tester setup.

    2. Isolate first failing metric bucket and scenario.

    3. Classify failure source: model, constraints, physical, or silicon.

    4. Prove mechanism with one reduced replay or targeted run.

    5. Apply smallest owner-controlled fix.

    6. Re-run timing, power, and quality regression matrix.

    Review memo template

    Diagram
    STAFF DFT REVIEW MEMO - MBIST & LBIST / Memory Repair Flow
    
    1. Symptom
       - Watched metric: repairable fail ratio, spare utilization, post-repair yield uplift
       - Failing scenario: <mode/lot/corner/program>
       - Pattern class: <scan/transition/compressed/BIST/JTAG>
       - Tags: <constraints, patterns, tester program, netlist>
    
    2. Mechanism hypothesis
       - Primary mechanism: Redundancy analysis maps diagnosed memory defects to spare rows/columns, trading area overhead for yield recovery.
       - Competing hypothesis: <constraint issue, model issue, physical issue, silicon issue>
       - Missing evidence: <report, replay, diagnosis trace>
    
    3. Proposed action
       - Minimal reversible change: <constraint fix, architecture tweak, pattern update>
       - Expected metric movement: <delta>
       - Regression risk: timing, power, quality, schedule
    
    4. Signoff
       - Re-run artifact: BIRA/BISR report, repair signature table, redundancy summary
       - Required owners: memory test owner, yield owner, DFT lead
       - Final decision: release, waive, rollback, or escalate

    DFT deep dive

    BIST value is realized only when insertion, diagnosis, and repair are tied to production flow.

    Concept diagram

    Diagram
    BIST FLOW
    
    insert MBIST/LBIST -> execute -> collect signatures -> diagnose/repair -> signoff

    Metric graph

    Diagram
    REPAIR EFFECT
    
    yield
      ^
      |      o pre-repair
      |             o post-repair
      +---------------------> lot

    Reports and artifacts

    • MBIST insertion coverage

    • repair signature report

    • LBIST resistant fault list

    • BIST release checklist

    Mini case study

    Fuse programming mismatch blocked repair activation; corrected bring-up script recovered expected yield uplift.

    Debug branches

    • Validate BIST reachability

    • Correlate fail maps to repair signatures

    • Audit in-field boot test budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Redundancy analysis maps diagnosed memory defects to spare rows/columns, trading area overhead for yield recovery.

    Metric: repairable fail ratio, spare utilization, post-repair yield uplift

    This content block can't be displayed here.

    Block type: unknown

    This content block can't be displayed here.

    Block type: unknown

    This content block can't be displayed here.

    Block type: unknown

    Previous

    206 / 493

    Next: Memory Repair Flow: Worked Example

    Up next

    Up nextMemory Repair Flow: Worked Example

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Memory Repair Flow: Mechanism
    • Memory Repair Flow: Inputs & Outputs
    • Memory Repair Flow: Pitfalls & Red Flags