Interview drills

Interview Drills for Memory Repair Flow focuses on repairable fail ratio, spare utilization, post-repair yield uplift. The goal is to convert metric movement into mechanism, owner, and release decision.

PROMPT
You observe repairable fail ratio, spare utilization, post-repair yield uplift on Memory Repair Flow. Walk through diagnosis and release decision.

STRONG ANSWER
1. States context and run tags.
2. Explains mechanism: Redundancy analysis maps diagnosed memory defects to spare rows/columns, trading area overhead for yield recovery.
3. Requests BIRA/BISR report, repair signature table, redundancy summary.
4. Proposes minimal fix and regression.

WEAK ANSWER
Jumps to tool switches without evidence quality, ownership, or regression plan.

Diagram to draw on the whiteboard

Repair flow

BIST fail bitmap -> redundancy analysis -> spare assignment -> fuse programming -> retest

Root-cause narrative

ROOT-CAUSE TREE - Memory Repair Flow

repairable fail ratio, spare utilization, post-repair yield uplift regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

DFT deep dive

BIST value is realized only when insertion, diagnosis, and repair are tied to production flow.

Concept diagram

BIST FLOW

insert MBIST/LBIST -> execute -> collect signatures -> diagnose/repair -> signoff

Metric graph

REPAIR EFFECT

yield
  ^
  |      o pre-repair
  |             o post-repair
  +---------------------> lot

Reports and artifacts

• MBIST insertion coverage

• repair signature report

• LBIST resistant fault list

• BIST release checklist

Mini case study

Fuse programming mismatch blocked repair activation; corrected bring-up script recovered expected yield uplift.

Debug branches

• Validate BIST reachability

• Correlate fail maps to repair signatures

• Audit in-field boot test budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Redundancy analysis maps diagnosed memory defects to spare rows/columns, trading area overhead for yield recovery.

Metric: repairable fail ratio, spare utilization, post-repair yield uplift