Silicon impact

Repair strategy and signature quality drive real yield outcomes.

Area drivers

• compression logic footprint

• hold buffers from scan paths

Power drivers

• shift toggling peaks

• capture burst stress

Timing impact

• test-clock skew

• shift/capture path sensitivity

PD consequences

• chain route detours

• placement hotspots near test logic

Verification burden

• pattern replay correlation

• diagnosis reproducibility

SILICON IMPACT - MBIST Integration
area/power/timing/yield tradeoff

Takeaways

• Signoff needs silicon evidence

• Ownership clarity accelerates closure

Design option snapshot

CHAIN BALANCE - MBIST Integration

chain length
  ^
  |      o        o
  |   o    o  o
  | o
  +-----------------------------> chain index

Tight spread reduces shift time and hold-fix burden.

DFT deep dive

BIST value is realized only when insertion, diagnosis, and repair are tied to production flow.

Concept diagram

BIST FLOW

insert MBIST/LBIST -> execute -> collect signatures -> diagnose/repair -> signoff

Metric graph

REPAIR EFFECT

yield
  ^
  |      o pre-repair
  |             o post-repair
  +---------------------> lot

Reports and artifacts

• MBIST insertion coverage

• repair signature report

• LBIST resistant fault list

• BIST release checklist

Mini case study

Fuse programming mismatch blocked repair activation; corrected bring-up script recovered expected yield uplift.

Debug branches

• Validate BIST reachability

• Correlate fail maps to repair signatures

• Audit in-field boot test budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

MBIST integrates controllers, wrappers, and access paths so embedded memories can be tested and diagnosed efficiently on tester.

Metric: memory BIST insertion coverage, MBIST controller reach, MBIST DRC count