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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
    • MBIST Integration
    • Memory Repair Flow
    • LBIST Overview
      • LBIST Overview: Mechanism
      • LBIST Overview: Inputs & Outputs
      • LBIST Overview: Reports & Metrics
      • LBIST Overview: Debug Playbook
      • LBIST Overview: Worked Example
      • LBIST Overview: Pitfalls & Red Flags
      • LBIST Overview: Interview Drills
      • LBIST Overview: Review Checklist
      • LBIST Overview: Theory Deep Dive
      • LBIST Overview: Design Space
      • LBIST Overview: Expanded Case Study
      • LBIST Overview: Step-by-Step Walkthrough
      • LBIST Overview: Comparison Matrix
      • LBIST Overview: Software / Programmer View
      • LBIST Overview: Silicon PPA Impact
    • BIST Signoff
    • MBIST & LBIST: Tricky Q&A
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹LBIST Overview
  1. Topics
  2. Design for Test
  3. MBIST & LBIST
  4. LBIST Overview
  5. LBIST Overview: Review Checklist

DFT / ATPG · All levels

LBIST Overview: Review Checklist

Review Checklist for LBIST Overview.

On this page

    Review checklist

    Review Checklist for LBIST Overview focuses on LBIST signature quality, random-pattern-resistant fault count, runtime budget. The goal is to convert metric movement into mechanism, owner, and release decision.

    • Run tags and scenario context are explicit.

    • Constraints and legality assumptions are documented.

    • Quality, timing, and test-power checks are included.

    • Diagnosis evidence supports residual-risk decision.

    • Owners signed: DFT architect, safety owner, product engineering owner.

    Signoff ownership

    Diagram
    OWNERSHIP MAP - LBIST Overview
    
    artifact              owner
    ----------------      -----------------
    architecture/report DFT architect
    constraints/setup   safety owner
    physical/test       product engineering owner
    
    Name an owner for each failing metric cluster.

    DFT deep dive

    BIST value is realized only when insertion, diagnosis, and repair are tied to production flow.

    Concept diagram

    Diagram
    BIST FLOW
    
    insert MBIST/LBIST -> execute -> collect signatures -> diagnose/repair -> signoff

    Metric graph

    Diagram
    REPAIR EFFECT
    
    yield
      ^
      |      o pre-repair
      |             o post-repair
      +---------------------> lot

    Reports and artifacts

    • MBIST insertion coverage

    • repair signature report

    • LBIST resistant fault list

    • BIST release checklist

    Mini case study

    Fuse programming mismatch blocked repair activation; corrected bring-up script recovered expected yield uplift.

    Debug branches

    • Validate BIST reachability

    • Correlate fail maps to repair signatures

    • Audit in-field boot test budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    LBIST uses on-chip pattern generation and signature compression for in-system logic test where external ATPG access is limited.

    Metric: LBIST signature quality, random-pattern-resistant fault count, runtime budget

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    See also

    • LBIST Overview: Mechanism
    • LBIST Overview: Inputs & Outputs
    • LBIST Overview: Reports & Metrics