Diagnosis & Yield Learning: Software / Programmer View

RTL / integration view

Unknown sources in RTL quickly become compression blind spots.

What teams feel

• Unexpected untestables

• clock/reset test-mode conflicts

RTL structure impact

• Scan hooks

• mode controls

• debug access gating

Tool interaction

• Synthesis transforms affecting scan paths

• clock-gating interaction

Mitigations

• DFT lint gates

• test-aware coding standards

• joint RTL/DFT reviews

RTL VIEW - Diagnosis & Yield Learning
// mode logic changed -> recheck controllability and constraints

Layer touch points

DFT OWNERSHIP LAYERS - Diagnosis & Yield Learning

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

Compression saves tester time only when diagnosis observability remains credible.

Concept diagram

COMPRESSION LOOP

EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

Metric graph

PATTERN vs COVERAGE

coverage up   -> pattern count up
compression up -> pattern count down (until aliasing risk)

Reports and artifacts

• compression ratio dashboard

• pattern count trend

• X-source report

• diagnosis bucket summary

Mini case study

Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

Debug branches

• Separate X issues from silicon defects

• Replay failing patterns uncompressed

• Track tester memory budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Fail logs and diagnosis map failing signatures back to likely defect sites, enabling systematic yield learning loops with design and process teams.

Metric: diagnosis resolution, top failing buckets, yield learning turnaround