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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
    • Compression Architectures
    • Pattern Volume Tradeoffs
    • Diagnosis & Yield Learning
      • Diagnosis & Yield Learning: Mechanism
      • Diagnosis & Yield Learning: Inputs & Outputs
      • Diagnosis & Yield Learning: Reports & Metrics
      • Diagnosis & Yield Learning: Debug Playbook
      • Diagnosis & Yield Learning: Worked Example
      • Diagnosis & Yield Learning: Pitfalls & Red Flags
      • Diagnosis & Yield Learning: Interview Drills
      • Diagnosis & Yield Learning: Review Checklist
      • Diagnosis & Yield Learning: Theory Deep Dive
      • Diagnosis & Yield Learning: Design Space
      • Diagnosis & Yield Learning: Expanded Case Study
      • Diagnosis & Yield Learning: Step-by-Step Walkthrough
      • Diagnosis & Yield Learning: Comparison Matrix
      • Diagnosis & Yield Learning: Software / Programmer View
      • Diagnosis & Yield Learning: Silicon PPA Impact
    • Compression Debug
    • Compression & Diagnosis: Tricky Q&A
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Diagnosis & Yield Learning
  1. Topics
  2. Design for Test
  3. Compression & Diagnosis
  4. Diagnosis & Yield Learning
  5. Diagnosis & Yield Learning: Pitfalls & Red Flags

DFT / ATPG · All levels

Diagnosis & Yield Learning: Pitfalls & Red Flags

Pitfalls & Red Flags for Diagnosis & Yield Learning.

On this page

    Pitfalls and red flags

    Pitfalls & Red Flags for Diagnosis & Yield Learning focuses on diagnosis resolution, top failing buckets, yield learning turnaround. The goal is to convert metric movement into mechanism, owner, and release decision.

    • Coverage improves while diagnosis quality degrades.

    • Pattern count drops but test escapes rise.

    • Shift timing passes while capture timing regresses.

    • Power fixes alter quality behavior without retest.

    • Owner handoff is unclear for recurring failures.

    Layer responsibility check

    Diagram
    DFT OWNERSHIP LAYERS - Diagnosis & Yield Learning
    
    layer              owns                         failure mode
    ----------------   --------------------------   -------------------------
    rtl/architecture   scanability hooks            uncontrollable logic
    atpg/constraints   legal pattern intent         aborts, low coverage
    physical/clocking  chain route + test clocks    shift hold/timing escapes
    tester/program     pattern apply integrity      false binning / bad fails
    quality signoff    release criteria             escapes or schedule slip

    DFT deep dive

    Compression saves tester time only when diagnosis observability remains credible.

    Concept diagram

    Diagram
    COMPRESSION LOOP
    
    EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

    Metric graph

    Diagram
    PATTERN vs COVERAGE
    
    coverage up   -> pattern count up
    compression up -> pattern count down (until aliasing risk)

    Reports and artifacts

    • compression ratio dashboard

    • pattern count trend

    • X-source report

    • diagnosis bucket summary

    Mini case study

    Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

    Debug branches

    • Separate X issues from silicon defects

    • Replay failing patterns uncompressed

    • Track tester memory budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Fail logs and diagnosis map failing signatures back to likely defect sites, enabling systematic yield learning loops with design and process teams.

    Metric: diagnosis resolution, top failing buckets, yield learning turnaround

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    See also

    • Diagnosis & Yield Learning: Mechanism
    • Diagnosis & Yield Learning: Inputs & Outputs
    • Diagnosis & Yield Learning: Reports & Metrics