Compression Debug turns DFT intent into measurable release confidence. Compression debug isolates whether failures come from EDT wiring, X-masking policy, clocking, or ATPG assumptions before blaming silicon defects. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.
When unknown/X inflation, compactor overflow incidents, pattern replay success rate moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?
DFT CLOSURE FLOW - Compression Debug
scan/test architecture
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v
ATPG constraints + fault models
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pattern generation + compression
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timing/power/physical validation
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silicon diagnosis and release signoff
Debug rule: always state metric, run tags, and owning team with any claim.Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.
compression architecture -> ATPG patterns -> fail logs -> diagnosis -> yield learningDFT FLOW - Compression Debug
scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
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controllability shift balance channel use coverage silicon correlation
Primary metric: unknown/X inflation, compactor overflow incidents, pattern replay success rateDFT OWNERSHIP LAYERS - Compression Debug
layer owns failure mode
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rtl/architecture scanability hooks uncontrollable logic
atpg/constraints legal pattern intent aborts, low coverage
physical/clocking chain route + test clocks shift hold/timing escapes
tester/program pattern apply integrity false binning / bad fails
quality signoff release criteria escapes or schedule slipPrimary metric: unknown/X inflation, compactor overflow incidents, pattern replay success rate.
Primary artifact: X-source trace, compactor status report, pattern replay logs.
Owners to bring into review: ATPG owner, DFT owner, silicon bring-up owner.
One failing signature and one reduced reproduction path.
Exact run tags for constraints, patterns, and tester program.
OWNERSHIP MAP - Compression Debug
artifact owner
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architecture/report ATPG owner
constraints/setup DFT owner
physical/test silicon bring-up owner
Name an owner for each failing metric cluster.Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.
State metric and run tags with every claim.
Connect every fix to a regression matrix.
Treat quality, timing, and power as coupled.
Coverage-centric decisions without legality checks.
Pattern changes without tester correlation.
Release calls without owner signoff.
Compression saves tester time only when diagnosis observability remains credible.
COMPRESSION LOOP
EDT/decompressor -> compressed patterns -> compactor responses -> diagnosisPATTERN vs COVERAGE
coverage up -> pattern count up
compression up -> pattern count down (until aliasing risk)compression ratio dashboard
pattern count trend
X-source report
diagnosis bucket summary
Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.
Separate X issues from silicon defects
Replay failing patterns uncompressed
Track tester memory budget
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.