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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
    • Compression Architectures
    • Pattern Volume Tradeoffs
    • Diagnosis & Yield Learning
    • Compression Debug
      • Compression Debug: Mechanism
      • Compression Debug: Inputs & Outputs
      • Compression Debug: Reports & Metrics
      • Compression Debug: Debug Playbook
      • Compression Debug: Worked Example
      • Compression Debug: Pitfalls & Red Flags
      • Compression Debug: Interview Drills
      • Compression Debug: Review Checklist
      • Compression Debug: Theory Deep Dive
      • Compression Debug: Design Space
      • Compression Debug: Expanded Case Study
      • Compression Debug: Step-by-Step Walkthrough
      • Compression Debug: Comparison Matrix
      • Compression Debug: Software / Programmer View
      • Compression Debug: Silicon PPA Impact
    • Compression & Diagnosis: Tricky Q&A
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Compression Debug
  1. Topics
  2. Design for Test
  3. Compression & Diagnosis
  4. Compression Debug
  5. Compression Debug: Inputs & Outputs

DFT / ATPG · All levels

Compression Debug: Inputs & Outputs

Inputs & Outputs for Compression Debug.

On this page

    Inputs and outputs contract

    Inputs & Outputs for Compression Debug focuses on unknown/X inflation, compactor overflow incidents, pattern replay success rate. The goal is to convert metric movement into mechanism, owner, and release decision.

    Treat these as a release contract. Ambiguity here creates expensive debug loops because teams optimize against different assumptions.

    Diagram
    INPUTS
      - scan/ATPG architecture and constraints
      - fault model and quality target policy
      - pattern generation config + tester limits
      - timing/power/physical assumptions
    
    OUTPUTS
      - quality metrics and closure status
      - signed artifacts and owner approvals
      - diagnosis evidence for residual risk
      - release, waiver, or escalation decision

    Flow sequence

    Diagram
    DFT FLOW - Compression Debug
    
    scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
          |                |                |            |             |
     controllability   shift balance    channel use   coverage     silicon correlation
    
    Primary metric: unknown/X inflation, compactor overflow incidents, pattern replay success rate

    Ownership map

    Diagram
    OWNERSHIP MAP - Compression Debug
    
    artifact              owner
    ----------------      -----------------
    architecture/report ATPG owner
    constraints/setup   DFT owner
    physical/test       silicon bring-up owner
    
    Name an owner for each failing metric cluster.

    DFT deep dive

    Compression saves tester time only when diagnosis observability remains credible.

    Concept diagram

    Diagram
    COMPRESSION LOOP
    
    EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

    Metric graph

    Diagram
    PATTERN vs COVERAGE
    
    coverage up   -> pattern count up
    compression up -> pattern count down (until aliasing risk)

    Reports and artifacts

    • compression ratio dashboard

    • pattern count trend

    • X-source report

    • diagnosis bucket summary

    Mini case study

    Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

    Debug branches

    • Separate X issues from silicon defects

    • Replay failing patterns uncompressed

    • Track tester memory budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Compression debug isolates whether failures come from EDT wiring, X-masking policy, clocking, or ATPG assumptions before blaming silicon defects.

    Metric: unknown/X inflation, compactor overflow incidents, pattern replay success rate

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    See also

    • Compression Debug: Debug Playbook
    • Compression Debug: Worked Example
    • Compression Debug: Pitfalls & Red Flags