Compression Debug: Silicon PPA Impact

Silicon impact

Compressed signatures are only useful when X behavior is controlled.

Area drivers

• compression logic footprint

• hold buffers from scan paths

Power drivers

• shift toggling peaks

• capture burst stress

Timing impact

• test-clock skew

• shift/capture path sensitivity

PD consequences

• chain route detours

• placement hotspots near test logic

Verification burden

• pattern replay correlation

• diagnosis reproducibility

SILICON IMPACT - Compression Debug
area/power/timing/yield tradeoff

Takeaways

• Signoff needs silicon evidence

• Ownership clarity accelerates closure

Design option snapshot

CHAIN BALANCE - Compression Debug

chain length
  ^
  |      o        o
  |   o    o  o
  | o
  +-----------------------------> chain index

Tight spread reduces shift time and hold-fix burden.

DFT deep dive

Compression saves tester time only when diagnosis observability remains credible.

Concept diagram

COMPRESSION LOOP

EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

Metric graph

PATTERN vs COVERAGE

coverage up   -> pattern count up
compression up -> pattern count down (until aliasing risk)

Reports and artifacts

• compression ratio dashboard

• pattern count trend

• X-source report

• diagnosis bucket summary

Mini case study

Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

Debug branches

• Separate X issues from silicon defects

• Replay failing patterns uncompressed

• Track tester memory budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Compression debug isolates whether failures come from EDT wiring, X-masking policy, clocking, or ATPG assumptions before blaming silicon defects.

Metric: unknown/X inflation, compactor overflow incidents, pattern replay success rate