Compression Architectures

What this topic teaches

Compression Architectures turns DFT intent into measurable release confidence. Compression inserts on-chip decompressors/compactors to reduce external tester pattern volume while preserving defect detection quality. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.

The senior-engineer question

When compression ratio, decompressor channel utilization, aliasing risk moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?

DFT CLOSURE FLOW - Compression Architectures

scan/test architecture
        |
        v
ATPG constraints + fault models
        |
        v
pattern generation + compression
        |
        v
timing/power/physical validation
        |
        v
silicon diagnosis and release signoff

Debug rule: always state metric, run tags, and owning team with any claim.

Picture the closure flow

Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.

Compression pipeline

ATE CH -> on-chip decompressor -> scan chains -> compactor -> ATE CH

higher compression ratio
  -> lower tester memory
  -> higher X-management complexity

Process sequence

DFT FLOW - Compression Architectures

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: compression ratio, decompressor channel utilization, aliasing risk

Ownership layers

DFT OWNERSHIP LAYERS - Compression Architectures

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

Evidence to collect

• Primary metric: compression ratio, decompressor channel utilization, aliasing risk.

• Primary artifact: compression architecture spec, channel map, alias analysis report.

• Owners to bring into review: DFT architect, ATPG owner, test engineering owner.

• One failing signature and one reduced reproduction path.

• Exact run tags for constraints, patterns, and tester program.

Ownership map

OWNERSHIP MAP - Compression Architectures

artifact              owner
----------------      -----------------
architecture/report DFT architect
constraints/setup   ATPG owner
physical/test       test engineering owner

Name an owner for each failing metric cluster.

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

• State metric and run tags with every claim.

• Connect every fix to a regression matrix.

• Treat quality, timing, and power as coupled.

Common pitfalls

• Coverage-centric decisions without legality checks.

• Pattern changes without tester correlation.

• Release calls without owner signoff.

DFT deep dive

Compression saves tester time only when diagnosis observability remains credible.

Concept diagram

COMPRESSION LOOP

EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

Metric graph

PATTERN vs COVERAGE

coverage up   -> pattern count up
compression up -> pattern count down (until aliasing risk)

Reports and artifacts

• compression ratio dashboard

• pattern count trend

• X-source report

• diagnosis bucket summary

Mini case study

Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

Debug branches

• Separate X issues from silicon defects

• Replay failing patterns uncompressed

• Track tester memory budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.