Compression Architectures: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for Compression Architectures focuses on compression ratio, decompressor channel utilization, aliasing risk. The goal is to convert metric movement into mechanism, owner, and release decision.

Treat these as a release contract. Ambiguity here creates expensive debug loops because teams optimize against different assumptions.

INPUTS
  - scan/ATPG architecture and constraints
  - fault model and quality target policy
  - pattern generation config + tester limits
  - timing/power/physical assumptions

OUTPUTS
  - quality metrics and closure status
  - signed artifacts and owner approvals
  - diagnosis evidence for residual risk
  - release, waiver, or escalation decision

Flow sequence

DFT FLOW - Compression Architectures

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: compression ratio, decompressor channel utilization, aliasing risk

Ownership map

OWNERSHIP MAP - Compression Architectures

artifact              owner
----------------      -----------------
architecture/report DFT architect
constraints/setup   ATPG owner
physical/test       test engineering owner

Name an owner for each failing metric cluster.

DFT deep dive

Compression saves tester time only when diagnosis observability remains credible.

Concept diagram

COMPRESSION LOOP

EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

Metric graph

PATTERN vs COVERAGE

coverage up   -> pattern count up
compression up -> pattern count down (until aliasing risk)

Reports and artifacts

• compression ratio dashboard

• pattern count trend

• X-source report

• diagnosis bucket summary

Mini case study

Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

Debug branches

• Separate X issues from silicon defects

• Replay failing patterns uncompressed

• Track tester memory budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Compression inserts on-chip decompressors/compactors to reduce external tester pattern volume while preserving defect detection quality.

Metric: compression ratio, decompressor channel utilization, aliasing risk