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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
    • Compression Architectures
      • Compression Architectures: Mechanism
      • Compression Architectures: Inputs & Outputs
      • Compression Architectures: Reports & Metrics
      • Compression Architectures: Debug Playbook
      • Compression Architectures: Worked Example
      • Compression Architectures: Pitfalls & Red Flags
      • Compression Architectures: Interview Drills
      • Compression Architectures: Review Checklist
      • Compression Architectures: Theory Deep Dive
      • Compression Architectures: Design Space
      • Compression Architectures: Expanded Case Study
      • Compression Architectures: Step-by-Step Walkthrough
      • Compression Architectures: Comparison Matrix
      • Compression Architectures: Software / Programmer View
      • Compression Architectures: Silicon PPA Impact
    • Pattern Volume Tradeoffs
    • Diagnosis & Yield Learning
    • Compression Debug
    • Compression & Diagnosis: Tricky Q&A
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Compression Architectures
  1. Topics
  2. Design for Test
  3. Compression & Diagnosis
  4. Compression Architectures
  5. Compression Architectures: Inputs & Outputs

DFT / ATPG · All levels

Compression Architectures: Inputs & Outputs

Inputs & Outputs for Compression Architectures.

On this page

    Inputs and outputs contract

    Inputs & Outputs for Compression Architectures focuses on compression ratio, decompressor channel utilization, aliasing risk. The goal is to convert metric movement into mechanism, owner, and release decision.

    Treat these as a release contract. Ambiguity here creates expensive debug loops because teams optimize against different assumptions.

    Diagram
    INPUTS
      - scan/ATPG architecture and constraints
      - fault model and quality target policy
      - pattern generation config + tester limits
      - timing/power/physical assumptions
    
    OUTPUTS
      - quality metrics and closure status
      - signed artifacts and owner approvals
      - diagnosis evidence for residual risk
      - release, waiver, or escalation decision

    Flow sequence

    Diagram
    DFT FLOW - Compression Architectures
    
    scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
          |                |                |            |             |
     controllability   shift balance    channel use   coverage     silicon correlation
    
    Primary metric: compression ratio, decompressor channel utilization, aliasing risk

    Ownership map

    Diagram
    OWNERSHIP MAP - Compression Architectures
    
    artifact              owner
    ----------------      -----------------
    architecture/report DFT architect
    constraints/setup   ATPG owner
    physical/test       test engineering owner
    
    Name an owner for each failing metric cluster.

    DFT deep dive

    Compression saves tester time only when diagnosis observability remains credible.

    Concept diagram

    Diagram
    COMPRESSION LOOP
    
    EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

    Metric graph

    Diagram
    PATTERN vs COVERAGE
    
    coverage up   -> pattern count up
    compression up -> pattern count down (until aliasing risk)

    Reports and artifacts

    • compression ratio dashboard

    • pattern count trend

    • X-source report

    • diagnosis bucket summary

    Mini case study

    Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

    Debug branches

    • Separate X issues from silicon defects

    • Replay failing patterns uncompressed

    • Track tester memory budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Compression inserts on-chip decompressors/compactors to reduce external tester pattern volume while preserving defect detection quality.

    Metric: compression ratio, decompressor channel utilization, aliasing risk

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    See also

    • Compression Architectures: Debug Playbook
    • Compression Architectures: Worked Example
    • Compression Architectures: Pitfalls & Red Flags