Compression Architectures: Interview Drills

Interview drills

Interview Drills for Compression Architectures focuses on compression ratio, decompressor channel utilization, aliasing risk. The goal is to convert metric movement into mechanism, owner, and release decision.

PROMPT
You observe compression ratio, decompressor channel utilization, aliasing risk on Compression Architectures. Walk through diagnosis and release decision.

STRONG ANSWER
1. States context and run tags.
2. Explains mechanism: Compression inserts on-chip decompressors/compactors to reduce external tester pattern volume while preserving defect detection quality.
3. Requests compression architecture spec, channel map, alias analysis report.
4. Proposes minimal fix and regression.

WEAK ANSWER
Jumps to tool switches without evidence quality, ownership, or regression plan.

Diagram to draw on the whiteboard

Compression pipeline

ATE CH -> on-chip decompressor -> scan chains -> compactor -> ATE CH

higher compression ratio
  -> lower tester memory
  -> higher X-management complexity

Root-cause narrative

ROOT-CAUSE TREE - Compression Architectures

compression ratio, decompressor channel utilization, aliasing risk regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

DFT deep dive

Compression saves tester time only when diagnosis observability remains credible.

Concept diagram

COMPRESSION LOOP

EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

Metric graph

PATTERN vs COVERAGE

coverage up   -> pattern count up
compression up -> pattern count down (until aliasing risk)

Reports and artifacts

• compression ratio dashboard

• pattern count trend

• X-source report

• diagnosis bucket summary

Mini case study

Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

Debug branches

• Separate X issues from silicon defects

• Replay failing patterns uncompressed

• Track tester memory budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Compression inserts on-chip decompressors/compactors to reduce external tester pattern volume while preserving defect detection quality.

Metric: compression ratio, decompressor channel utilization, aliasing risk