Compression Architectures: Worked Example

Worked example

Worked Example for Compression Architectures focuses on compression ratio, decompressor channel utilization, aliasing risk. The goal is to convert metric movement into mechanism, owner, and release decision.

A release review shows regression on compression ratio, decompressor channel utilization, aliasing risk. The strongest first move is to freeze evidence, isolate one failing bucket, and prove mechanism before changing flow knobs.

Sequence under inspection

DFT FLOW - Compression Architectures

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: compression ratio, decompressor channel utilization, aliasing risk

Compression pipeline

ATE CH -> on-chip decompressor -> scan chains -> compactor -> ATE CH

higher compression ratio
  -> lower tester memory
  -> higher X-management complexity

1. Capture failing report and exact run tags.

2. Tag scenario (mode, lot/corner, pattern class).

3. Trace first dependency that changed.

4. Compare against compression architecture spec, channel map, alias analysis report.

5. Choose one reversible fix and predefine regression checks.

Did the fix work?

BEFORE / AFTER - Compression Architectures

metric quality
  ^
  |                    --- release target
  |      o regressed
  |           o baseline
  |                o after fix
  +-------------------------------> closure iteration

Prove quality, timing, and test-power all moved safely.

DFT deep dive

Compression saves tester time only when diagnosis observability remains credible.

Concept diagram

COMPRESSION LOOP

EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

Metric graph

PATTERN vs COVERAGE

coverage up   -> pattern count up
compression up -> pattern count down (until aliasing risk)

Reports and artifacts

• compression ratio dashboard

• pattern count trend

• X-source report

• diagnosis bucket summary

Mini case study

Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

Debug branches

• Separate X issues from silicon defects

• Replay failing patterns uncompressed

• Track tester memory budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Compression inserts on-chip decompressors/compactors to reduce external tester pattern volume while preserving defect detection quality.

Metric: compression ratio, decompressor channel utilization, aliasing risk