Compression Architectures: Expanded Case Study

Extended case study

Release review: compression ratio, decompressor channel utilization, aliasing risk regresses after a test-flow update touching Compression Architectures.

Background

Team had prior signoff, then a new program/config introduced regressions in selected buckets.

Symptoms observed

• compression ratio, decompressor channel utilization, aliasing risk regression

• Mismatch between simulation and tester

• Escalation without clear owner

Investigation timeline

1. Hour 0: freeze pattern set, constraints, and tester program tags

2. Hour 1: isolate first failing bucket by mode/lot

3. Hour 2: verify legality and constraints assumptions

4. Hour 3: correlate with physical/timing/power context

5. Hour 4: choose minimal reversible fix

6. Hour 5: run full signoff regression matrix

7. Hour 6: publish decision memo and owners

Root cause

Root cause tied to Compression Architectures: Compression inserts on-chip decompressors/compactors to reduce external tester pattern volume while preserving defect detection quality.

Fix and validation

• Apply bounded fix with owner

• Re-run compression architecture spec, channel map, alias analysis report

• Re-validate quality, timing, and test power

Lessons learned

• Tag every run artifact

• Mechanism first, command second

• Close with explicit release decision

CASE STUDY - Compression Architectures
baseline metric / regressed metric / post-fix metric

Sequence under stress

DFT FLOW - Compression Architectures

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: compression ratio, decompressor channel utilization, aliasing risk

DFT deep dive

Compression saves tester time only when diagnosis observability remains credible.

Concept diagram

COMPRESSION LOOP

EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

Metric graph

PATTERN vs COVERAGE

coverage up   -> pattern count up
compression up -> pattern count down (until aliasing risk)

Reports and artifacts

• compression ratio dashboard

• pattern count trend

• X-source report

• diagnosis bucket summary

Mini case study

Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

Debug branches

• Separate X issues from silicon defects

• Replay failing patterns uncompressed

• Track tester memory budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Compression inserts on-chip decompressors/compactors to reduce external tester pattern volume while preserving defect detection quality.

Metric: compression ratio, decompressor channel utilization, aliasing risk