Compression Architectures: Theory Deep Dive

Foundational theory

Compression Architectures is central to Compression & Diagnosis. Compression inserts on-chip decompressors/compactors to reduce external tester pattern volume while preserving defect detection quality. Senior DFT engineers tie metric movement to architecture assumptions, constraints, and silicon evidence rather than isolated tool output.

Core concepts explained

• Compression inserts on-chip decompressors/compactors to reduce external tester pattern volume while preserving defect detection quality.

• Primary metric: compression ratio, decompressor channel utilization, aliasing risk

• Primary artifact: compression architecture spec, channel map, alias analysis report

• Owners: DFT architect, ATPG owner, test engineering owner

• Controllability and observability must be explicit

• Production-quality requires reproducible pattern and tester tags

Why this matters at release

At release, Compression Architectures issues can create coverage escapes, unstable production bins, or long debug loops. Compression is a quality-and-cost optimization, not just a ratio target.

Mental model

ATE CH -> on-chip decompressor -> scan chains -> compactor -> ATE CH

higher compression ratio
  -> lower tester memory
  -> higher X-management complexity

Worked intuition

1. Name failing metric and scenario context (mode, lot/corner, program).

2. Open compression ratio, decompressor channel utilization, aliasing risk trend and isolate dominant failing bucket.

3. Trace architecture assumptions and legality constraints.

4. Check compression, clocking, and unknown handling dependencies.

5. Collect compression architecture spec, channel map, alias analysis report and confirm run tags.

6. Classify issue: model/constraint, physical/test setup, or real defect signal.

7. Propose minimal fix and list timing/power/quality regression checks.

Common misconceptions

• Coverage percent alone proves release readiness.

• More compression always means better outcome.

• Silicon mismatch can be debugged without pattern/tester traceability.

• Shift timing and test power can be signed independently.

Visual reinforcement

Compression pipeline

ATE CH -> on-chip decompressor -> scan chains -> compactor -> ATE CH

higher compression ratio
  -> lower tester memory
  -> higher X-management complexity

Layer responsibilities

DFT OWNERSHIP LAYERS - Compression Architectures

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

Compression saves tester time only when diagnosis observability remains credible.

Concept diagram

COMPRESSION LOOP

EDT/decompressor -> compressed patterns -> compactor responses -> diagnosis

Metric graph

PATTERN vs COVERAGE

coverage up   -> pattern count up
compression up -> pattern count down (until aliasing risk)

Reports and artifacts

• compression ratio dashboard

• pattern count trend

• X-source report

• diagnosis bucket summary

Mini case study

Compactor overflow plus unknown inflation caused false diagnosis; masking policy and channel map corrected.

Debug branches

• Separate X issues from silicon defects

• Replay failing patterns uncompressed

• Track tester memory budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Theory reinforcement

Compression is a quality-and-cost optimization, not just a ratio target.