DFT Interview Q&A Bank

What this topic teaches

DFT Interview Q&A Bank turns DFT intent into measurable release confidence. A curated Q&A bank builds reusable answers around scan, ATPG, BIST, JTAG, and test-signoff judgment under ambiguity. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.

The senior-engineer question

When breadth of scenario coverage, answer depth consistency, trap avoidance rate moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?

DFT CLOSURE FLOW - DFT Interview Q&A Bank

scan/test architecture
        |
        v
ATPG constraints + fault models
        |
        v
pattern generation + compression
        |
        v
timing/power/physical validation
        |
        v
silicon diagnosis and release signoff

Debug rule: always state metric, run tags, and owning team with any claim.

Picture the closure flow

Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.

Interview flow

prompt -> mechanism -> metric -> artifact -> decision

Process sequence

DFT FLOW - DFT Interview Q&A Bank

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: breadth of scenario coverage, answer depth consistency, trap avoidance rate

Ownership layers

DFT OWNERSHIP LAYERS - DFT Interview Q&A Bank

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

Evidence to collect

• Primary metric: breadth of scenario coverage, answer depth consistency, trap avoidance rate.

• Primary artifact: Q&A bank, trap catalog, review scorecard.

• Owners to bring into review: candidate, mentor, DFT panel.

• One failing signature and one reduced reproduction path.

• Exact run tags for constraints, patterns, and tester program.

Ownership map

OWNERSHIP MAP - DFT Interview Q&A Bank

artifact              owner
----------------      -----------------
architecture/report candidate
constraints/setup   mentor
physical/test       DFT panel

Name an owner for each failing metric cluster.

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

• State metric and run tags with every claim.

• Connect every fix to a regression matrix.

• Treat quality, timing, and power as coupled.

Common pitfalls

• Coverage-centric decisions without legality checks.

• Pattern changes without tester correlation.

• Release calls without owner signoff.

Q&A drill guide

METRIC -> MECHANISM -> EVIDENCE -> FIX -> REGRESSION

Sketch while answering

INTERVIEW ANSWER LOOP

state metric -> explain mechanism -> request evidence -> propose fix -> list regression

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.