Scenario: Silicon Mismatch

What this topic teaches

Scenario: Silicon Mismatch turns DFT intent into measurable release confidence. Silicon mismatch scenarios test whether engineers can correlate ATPG assumptions, tester setup, and physical behavior before escalating. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.

The senior-engineer question

When silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?

DFT CLOSURE FLOW - Scenario: Silicon Mismatch

scan/test architecture
        |
        v
ATPG constraints + fault models
        |
        v
pattern generation + compression
        |
        v
timing/power/physical validation
        |
        v
silicon diagnosis and release signoff

Debug rule: always state metric, run tags, and owning team with any claim.

Picture the closure flow

Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.

Silicon mismatch loop

ATE fail -> replay -> diagnosis -> lot/corner cluster -> root cause -> corrective action

Process sequence

DFT FLOW - Scenario: Silicon Mismatch

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation

Ownership layers

DFT OWNERSHIP LAYERS - Scenario: Silicon Mismatch

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

Evidence to collect

• Primary metric: silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation.

• Primary artifact: failing pattern log, diagnosis trace, silicon correlation memo.

• Owners to bring into review: silicon bring-up owner, DFT owner, ATE owner.

• One failing signature and one reduced reproduction path.

• Exact run tags for constraints, patterns, and tester program.

Ownership map

OWNERSHIP MAP - Scenario: Silicon Mismatch

artifact              owner
----------------      -----------------
architecture/report silicon bring-up owner
constraints/setup   DFT owner
physical/test       ATE owner

Name an owner for each failing metric cluster.

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

• State metric and run tags with every claim.

• Connect every fix to a regression matrix.

• Treat quality, timing, and power as coupled.

Common pitfalls

• Coverage-centric decisions without legality checks.

• Pattern changes without tester correlation.

• Release calls without owner signoff.

DFT deep dive

Senior DFT interviews test tradeoff judgment under imperfect data.

Concept diagram

INTERVIEW ANSWER LOOP

state metric -> explain mechanism -> request evidence -> propose fix -> list regression

Metric graph

ANSWER QUALITY

mechanism clarity + ownership clarity + regression discipline

Reports and artifacts

• whiteboard rubric

• scenario scorecard

• trap checklist

• follow-up depth index

Mini case study

Candidate improved from tool-only answers to mechanism-first narratives by using metric->artifact->decision template.

Debug branches

• Always state assumptions

• Name cross-team owners

• Discuss risk and fallback plan

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.