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Scenario: Silicon Mismatch: Expanded Case Study

Expanded Case Study for Scenario: Silicon Mismatch.

Extended case study

Release review: silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation regresses after a test-flow update touching Scenario: Silicon Mismatch.

Background

Team had prior signoff, then a new program/config introduced regressions in selected buckets.

Symptoms observed

  • silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation regression

  • Mismatch between simulation and tester

  • Escalation without clear owner

Investigation timeline

  1. Hour 0: freeze pattern set, constraints, and tester program tags

  2. Hour 1: isolate first failing bucket by mode/lot

  3. Hour 2: verify legality and constraints assumptions

  4. Hour 3: correlate with physical/timing/power context

  5. Hour 4: choose minimal reversible fix

  6. Hour 5: run full signoff regression matrix

  7. Hour 6: publish decision memo and owners

Root cause

Root cause tied to Scenario: Silicon Mismatch: Silicon mismatch scenarios test whether engineers can correlate ATPG assumptions, tester setup, and physical behavior before escalating.

Fix and validation

  • Apply bounded fix with owner

  • Re-run failing pattern log, diagnosis trace, silicon correlation memo

  • Re-validate quality, timing, and test power

Lessons learned

  • Tag every run artifact

  • Mechanism first, command second

  • Close with explicit release decision

diagram
CASE STUDY - Scenario: Silicon Mismatch
baseline metric / regressed metric / post-fix metric

Sequence under stress

diagram
DFT FLOW - Scenario: Silicon Mismatch

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation

DFT deep dive

Senior DFT interviews test tradeoff judgment under imperfect data.

Concept diagram

diagram
INTERVIEW ANSWER LOOP

state metric -> explain mechanism -> request evidence -> propose fix -> list regression

Metric graph

diagram
ANSWER QUALITY

mechanism clarity + ownership clarity + regression discipline

Reports and artifacts

  • whiteboard rubric

  • scenario scorecard

  • trap checklist

  • follow-up depth index

Mini case study

Candidate improved from tool-only answers to mechanism-first narratives by using metric->artifact->decision template.

Debug branches

  • Always state assumptions

  • Name cross-team owners

  • Discuss risk and fallback plan

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

  • State metric, lot/corner context, and pattern tag with every claim.

  • Treat timing, power, and quality as one signoff problem.

Common pitfalls

  • Chasing coverage without legality checks.

  • Ignoring test-power side effects of pattern changes.

  • Debugging silicon without reproducible tags.

Principal DFT review addendum

Silicon mismatch scenarios test whether engineers can correlate ATPG assumptions, tester setup, and physical behavior before escalating.

Metric: silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation