Scenario: Silicon Mismatch: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for Scenario: Silicon Mismatch focuses on silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation. The goal is to convert metric movement into mechanism, owner, and release decision.

Treat these as a release contract. Ambiguity here creates expensive debug loops because teams optimize against different assumptions.

INPUTS
  - scan/ATPG architecture and constraints
  - fault model and quality target policy
  - pattern generation config + tester limits
  - timing/power/physical assumptions

OUTPUTS
  - quality metrics and closure status
  - signed artifacts and owner approvals
  - diagnosis evidence for residual risk
  - release, waiver, or escalation decision

Flow sequence

DFT FLOW - Scenario: Silicon Mismatch

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation

Ownership map

OWNERSHIP MAP - Scenario: Silicon Mismatch

artifact              owner
----------------      -----------------
architecture/report silicon bring-up owner
constraints/setup   DFT owner
physical/test       ATE owner

Name an owner for each failing metric cluster.

DFT deep dive

Senior DFT interviews test tradeoff judgment under imperfect data.

Concept diagram

INTERVIEW ANSWER LOOP

state metric -> explain mechanism -> request evidence -> propose fix -> list regression

Metric graph

ANSWER QUALITY

mechanism clarity + ownership clarity + regression discipline

Reports and artifacts

• whiteboard rubric

• scenario scorecard

• trap checklist

• follow-up depth index

Mini case study

Candidate improved from tool-only answers to mechanism-first narratives by using metric->artifact->decision template.

Debug branches

• Always state assumptions

• Name cross-team owners

• Discuss risk and fallback plan

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Silicon mismatch scenarios test whether engineers can correlate ATPG assumptions, tester setup, and physical behavior before escalating.

Metric: silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation