Scenario: Silicon Mismatch: Debug Playbook

Debug playbook

Debug Playbook for Scenario: Silicon Mismatch focuses on silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation. The goal is to convert metric movement into mechanism, owner, and release decision.

Debug aims to find the first incorrect assumption, not the loudest downstream symptom. Start with reproducibility and ownership.

Root-cause tree

ROOT-CAUSE TREE - Scenario: Silicon Mismatch

silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

1. Freeze run tags for patterns, constraints, and tester setup.

2. Isolate first failing metric bucket and scenario.

3. Classify failure source: model, constraints, physical, or silicon.

4. Prove mechanism with one reduced replay or targeted run.

5. Apply smallest owner-controlled fix.

6. Re-run timing, power, and quality regression matrix.

Review memo template

STAFF DFT REVIEW MEMO - DFT Interview Prep / Scenario: Silicon Mismatch

1. Symptom
   - Watched metric: silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation
   - Failing scenario: <mode/lot/corner/program>
   - Pattern class: <scan/transition/compressed/BIST/JTAG>
   - Tags: <constraints, patterns, tester program, netlist>

2. Mechanism hypothesis
   - Primary mechanism: Silicon mismatch scenarios test whether engineers can correlate ATPG assumptions, tester setup, and physical behavior before escalating.
   - Competing hypothesis: <constraint issue, model issue, physical issue, silicon issue>
   - Missing evidence: <report, replay, diagnosis trace>

3. Proposed action
   - Minimal reversible change: <constraint fix, architecture tweak, pattern update>
   - Expected metric movement: <delta>
   - Regression risk: timing, power, quality, schedule

4. Signoff
   - Re-run artifact: failing pattern log, diagnosis trace, silicon correlation memo
   - Required owners: silicon bring-up owner, DFT owner, ATE owner
   - Final decision: release, waive, rollback, or escalate

DFT deep dive

Senior DFT interviews test tradeoff judgment under imperfect data.

Concept diagram

INTERVIEW ANSWER LOOP

state metric -> explain mechanism -> request evidence -> propose fix -> list regression

Metric graph

ANSWER QUALITY

mechanism clarity + ownership clarity + regression discipline

Reports and artifacts

• whiteboard rubric

• scenario scorecard

• trap checklist

• follow-up depth index

Mini case study

Candidate improved from tool-only answers to mechanism-first narratives by using metric->artifact->decision template.

Debug branches

• Always state assumptions

• Name cross-team owners

• Discuss risk and fallback plan

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Silicon mismatch scenarios test whether engineers can correlate ATPG assumptions, tester setup, and physical behavior before escalating.

Metric: silicon fail reproducibility, diagnosis confidence, lab-to-ATE correlation