Test-Mode SDC: Expanded Case Study

Extended case study

Release review: test SDC completeness, false test-path violations, test constraint audit score regresses after a test-flow update touching Test-Mode SDC.

Background

Team had prior signoff, then a new program/config introduced regressions in selected buckets.

Symptoms observed

• test SDC completeness, false test-path violations, test constraint audit score regression

• Mismatch between simulation and tester

• Escalation without clear owner

Investigation timeline

1. Hour 0: freeze pattern set, constraints, and tester program tags

2. Hour 1: isolate first failing bucket by mode/lot

3. Hour 2: verify legality and constraints assumptions

4. Hour 3: correlate with physical/timing/power context

5. Hour 4: choose minimal reversible fix

6. Hour 5: run full signoff regression matrix

7. Hour 6: publish decision memo and owners

Root cause

Root cause tied to Test-Mode SDC: Dedicated test SDC captures scan clocks, test enables, and exceptions needed to analyze shift and capture behavior correctly.

Fix and validation

• Apply bounded fix with owner

• Re-run test-mode SDC, constraint audit report, test path summary

• Re-validate quality, timing, and test power

Lessons learned

• Tag every run artifact

• Mechanism first, command second

• Close with explicit release decision

CASE STUDY - Test-Mode SDC
baseline metric / regressed metric / post-fix metric

Sequence under stress

DFT FLOW - Test-Mode SDC

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: test SDC completeness, false test-path violations, test constraint audit score

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

• test-mode STA report

• shift/capture split

• test power IR map

• waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

• Tag test and functional corners separately

• Check hold in shift mode

• Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Dedicated test SDC captures scan clocks, test enables, and exceptions needed to analyze shift and capture behavior correctly.

Metric: test SDC completeness, false test-path violations, test constraint audit score