DFT / ATPG · All levels

Test-Mode SDC: Comparison Matrix

Comparison Matrix for Test-Mode SDC.

Comparison matrix

Shift speed, capture strategy, and pattern scheduling trade risk and throughput.

diagram

+------------------+----------------+----------------+----------------+
| Approach         | Strength       | Weakness       | Best when      |
+------------------+----------------+----------------+----------------+
| Conservative     | safe           | higher cost    | ramp-sensitive |
| Balanced         | practical      | needs rigor    | production     |
| Aggressive       | fast           | escape risk    | schedule pressure |
| Architecture     | durable        | slow           | repeated pain  |
+------------------+----------------+----------------+----------------+

When to choose each approach

Tie approach to product risk and tester constraints

Interview traps

Optimizing one metric only
No regression ownership

Evidence comparison

diagram

DFT EVIDENCE MATRIX - Test-Mode SDC

+-------------------+------------------------+--------------------------+-------------------------+
| Evidence           | Tells you              | Does not prove           | Next action             |
+-------------------+------------------------+--------------------------+-------------------------+
| coverage report    | fault detect trends    | silicon root cause       | inspect bucket details  |
| pattern diff       | generation changes     | architecture quality     | replay suspect patterns |
| timing/power report| test closure margin    | diagnosis confidence     | correlate fail logs     |
| diagnosis summary  | likely defect classes  | ownership decision       | assign action owner     |
| signoff checklist  | process completeness   | correctness of evidence  | peer review artifacts   |
+-------------------+------------------------+--------------------------+-------------------------+

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

diagram

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

test-mode STA report
shift/capture split
test power IR map
waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

Tag test and functional corners separately
Check hold in shift mode
Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.

Common pitfalls

Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.

Principal DFT review addendum

Dedicated test SDC captures scan clocks, test enables, and exceptions needed to analyze shift and capture behavior correctly.

Metric: test SDC completeness, false test-path violations, test constraint audit score

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