Test-Mode SDC: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for Test-Mode SDC focuses on test SDC completeness, false test-path violations, test constraint audit score. The goal is to convert metric movement into mechanism, owner, and release decision.

Treat these as a release contract. Ambiguity here creates expensive debug loops because teams optimize against different assumptions.

INPUTS
  - scan/ATPG architecture and constraints
  - fault model and quality target policy
  - pattern generation config + tester limits
  - timing/power/physical assumptions

OUTPUTS
  - quality metrics and closure status
  - signed artifacts and owner approvals
  - diagnosis evidence for residual risk
  - release, waiver, or escalation decision

Flow sequence

DFT FLOW - Test-Mode SDC

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: test SDC completeness, false test-path violations, test constraint audit score

Ownership map

OWNERSHIP MAP - Test-Mode SDC

artifact              owner
----------------      -----------------
architecture/report STA owner
constraints/setup   DFT owner
physical/test       ATPG owner

Name an owner for each failing metric cluster.

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

• test-mode STA report

• shift/capture split

• test power IR map

• waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

• Tag test and functional corners separately

• Check hold in shift mode

• Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Dedicated test SDC captures scan clocks, test enables, and exceptions needed to analyze shift and capture behavior correctly.

Metric: test SDC completeness, false test-path violations, test constraint audit score