Test-Mode SDC: Interview Drills

Interview drills

Interview Drills for Test-Mode SDC focuses on test SDC completeness, false test-path violations, test constraint audit score. The goal is to convert metric movement into mechanism, owner, and release decision.

PROMPT
You observe test SDC completeness, false test-path violations, test constraint audit score on Test-Mode SDC. Walk through diagnosis and release decision.

STRONG ANSWER
1. States context and run tags.
2. Explains mechanism: Dedicated test SDC captures scan clocks, test enables, and exceptions needed to analyze shift and capture behavior correctly.
3. Requests test-mode SDC, constraint audit report, test path summary.
4. Proposes minimal fix and regression.

WEAK ANSWER
Jumps to tool switches without evidence quality, ownership, or regression plan.

Diagram to draw on the whiteboard

Test SDC contract

test clocks + test enables + mode exceptions
    -> shift/capture timing checks
    -> legal test closure

Root-cause narrative

ROOT-CAUSE TREE - Test-Mode SDC

test SDC completeness, false test-path violations, test constraint audit score regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

• test-mode STA report

• shift/capture split

• test power IR map

• waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

• Tag test and functional corners separately

• Check hold in shift mode

• Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Dedicated test SDC captures scan clocks, test enables, and exceptions needed to analyze shift and capture behavior correctly.

Metric: test SDC completeness, false test-path violations, test constraint audit score