Test-Mode SDC: Reports & Metrics

Reports and metrics

Reports & Metrics for Test-Mode SDC focuses on test SDC completeness, false test-path violations, test constraint audit score. The goal is to convert metric movement into mechanism, owner, and release decision.

A report should support a release decision for test SDC completeness, false test-path violations, test constraint audit score. One headline number is rarely enough without setup tags and bucket-level evidence.

Metric movement

METRIC GRAPH - test SDC completeness, false test-path violations, test constraint audit score

quality metric
  ^
  |                         target
  |                       - - - - - - -
  |                  o after fix + regression
  |              o
  |         o baseline
  |    o regressed run
  +--------------------------------------> closure iteration
    input audit     focused fix      signoff review

Readout:
  - explain what moved, why it moved, and who approved it

Distribution view

PATTERN HISTOGRAM - Test-Mode SDC

pattern count
  |      ***
  |    *******
  |  ***********
  |*************  <- high-volume tail (optimize here)
  +--------------------> pattern buckets
   smoke  stuck-at  transition  diagnosis

Balance quality and tester limits together.

• Track test SDC completeness, false test-path violations, test constraint audit score by context and pattern class.

• Review trend and bucket detail together.

• Keep quality, timing, and power metrics in one dashboard.

• Store each metric next to the artifact and run tag.

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

• test-mode STA report

• shift/capture split

• test power IR map

• waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

• Tag test and functional corners separately

• Check hold in shift mode

• Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Reading reports